ICALEPCS2019 - List of Keywords (FPGA)

Paper	Title	Other Keywords	Page
MOPHA049	Test-bench Design for New Beam Instrumentation Electronics at CERN	instrumentation, hardware, electron, electronics	323
	M. Gonzalez-Berges, J.O. Robinson, M. Saccani, V. Schramm, M.A. Stachon CERN, Meyrin, Switzerland
	The Beam Instrumentation group has designed a new general-purpose VME acquisition board that will serve as the basis for the design of new instruments and will be used in the renovation of existing systems in the future. Around 1200 boards have been produced. They underwent validation, environmental stress screening and run-in tests to ensure their performance and long term reliability. This allowed to identify potential issues at an early stage and mitigate them, minimizing future interventions and downtime. A dedicated test-bench was designed to drive the tests and continuously monitor the board functionality. One board has more than 45 functions including memories, high speed serial links and a variety of diagnostics. The test-bench was fully integrated with the CERN asset management system to allow lifecycle management from the initial production phase. The data captured during these tests was stored and analyzed regularly to find sources of failures. This was the first time that such a complete test-bench has been used. This paper presents all the details of the test-bench design and implementation.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA049
About •	paper received ※ 30 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA076	Timing System Upgrade for Medical Linear Accelerator Project at SLRI	timing, hardware, GUI, electron	392
	R. Rujanakraikarn, P. Koonpong, S. Tesprasitte SLRI, Nakhon Ratchasima, Thailand
	A prototype of 6 MeV medical linear accelerator has been under development at Synchrotron Light Research Institute (SLRI). Several subsystems of the machine have been carefully designed and tested to prepare for x-ray generation. To maintain proper operation of the machine, pulse signals are generated to synchronize various subsystems. The timing system, based on the previous version designed on Xilinx Spartan-3 FPGA, is upgraded with better timing resolution, easier configuration with more timing channels, and future expansion of the system. A new LabVIEW GUI is also designed with more details on timing parameters for easy customization. The result of this new design is satisfactorily achieved with the resolution of 10 nanoseconds per time step and up to 15 synchronized timing channels implemented on two FPGA modules.
	Poster MOPHA076 [0.727 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA076
About •	paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA137	Timing Synchronization and Controls Integration for ESS Detector Readout	detector, EPICS, controls, timing	547
	W. Smith STFC/DL, Daresbury, Warrington, Cheshire, United Kingdom S. Alcock, J.M.C. Nilsson ESS, Lund, Sweden
	The European Spallation Source (ESS) is a new facility being built in Lund, Sweden, which when finished will be the world’s most powerful neutron source. STFC has an in-kind project with the Detector group at ESS to provide timing and control systems integration for the detector data readout system. This paper describes how time is synchronised and distributed to the readout system from the ESS timing system, and how EPICS is used to implement a controls interface exposing the functionality of detector front ends.
	Poster MOPHA137 [1.180 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA137
About •	paper received ※ 30 September 2019 paper accepted ※ 09 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA152	Use of Multi-Network Fieldbus for Integration of Low-Level Intelligent Controller Within Control Architecture of Fast Pulsed System at CERN	controls, network, interface, Ethernet	589
	N. Voumard, C. Boucly, M.P. Pimentel, L. Strobino, P. Van Trappen CERN, Geneva, Switzerland
	Fieldbuses and Industrial Ethernet networks are extensively used for the control of fast-pulsed magnets at CERN. With the ongoing trend to develop increasingly more complex low-level intelligent controllers near to the actuators and sensors, the flexibility to integrate these within different control architectures grows in importance. In order to reduce development efforts and keep the fieldbus choice open, a multi-network field-bus technology has been selected for the network interfacing part of the controllers. Such an approach has been successfully implemented for several projects such as the development of high voltage capacitor chargers/dischargers, the surveillance of floating solid-state switch and the monitoring of a power triggering system that, today, are interfaced either to PROFIBUS-DP or PROFINET networks. The integration of various fieldbus interfaces within the controller and the required embedded software/gateware to manage to network communication are presented. The gain in flexibility, modularity and openness obtained through this approach is also reviewed.
	Poster MOPHA152 [0.587 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA152
About •	paper received ※ 27 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA153	SoC Technology for Embedded Control and Interlocking Within Fast Pulsed Systems at CERN	controls, software, hardware, real-time	592
	P. Van Trappen, E. Carlier, M. Gauthier, N. Magnin, E.J. Oltedal, J. Schipper CERN, Geneva, Switzerland
	The control of pulsed systems at CERN requires often the use of fast digital electronics to perform tight timing control and fast protection of high-voltage pulsed generators. For the implementation of such functionalities, a FPGA is the perfect candidate for the digital logic, however with limited integration potential within the control system. The market push for integrated devices, so called System on a Chip (SoC) - a tightly coupled ARM processing system and specific programmable logic in a single device, has allowed a better integration of the various components required for the control of pulsed systems. This technology is used for the implementation of fast switch interlocking logic, integrated within the CERN control framework by using embedded Linux running a Snap7 server. It is also used for the implementation of a lower-tier communication bridge between a front-end computer and a high fan-out multiplexing programmable logic for timing and analogue low-level control. This paper presents these two projects where the SoC technology has been deployed and discusses possible further applications within distributed real-time control architecture for distributed pulsed systems.
	Poster MOPHA153 [0.828 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA153
About •	paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA156	The Linux Device Driver Framework for High-Throughput Lossless Data Streaming Applications	Linux, software, interface, neutron	602
	K. Vodopivec, J.E. Breeding ORNL, Oak Ridge, Tennessee, USA J.W. Sinclair ORNL RAD, Oak Ridge, Tennessee, USA
	Funding: This work was supported by the U.S. Department of Energy under contract DE-AC0500OR22725. Many applications in experimental physics facilities require custom hardware solutions to control process parameters or to acquire data at high rates with high integrity. These hardware solutions typically require custom software implementations. The neutron scattering detectors at the Spallation Neutron Source at ORNL* implement custom protocols over optical fiber connected to a PCI express based read-out board. A dedicated kernel device driver provides an interface to the software application and must be able to sustain data bursts from a pulsed source while acquiring data for long periods of time. The same optical channel is also used as low-latency communication link to detector electronics for configuration and real time fault detection. This paper presents a Linux device driver design, implementation challenges in a low-latency high-throughput setup, real use case benchmarks and importance of clean application programming interface for seamless integration in control systems. This software implementation was developed as a generic framework and has been extended beyond neutron data acquisition. It is suitable to diverse applications where it allows for rapid FPGA development. *Oak Ridge National Laboratory
	Poster MOPHA156 [4.163 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA156
About •	paper received ※ 02 October 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP01	Hardware-in-the-Loop Testing of Accelerator Firmware	software, hardware, controls, LLRF	659
	C. Serrano, M. Betz, L.R. Doolittle, S. Paiagua, V.K. Vytla LBNL, Berkeley, California, USA
	Continuous Integration (CI) is widely used in industry, especially in the software world. Here we propose a combination of CI processes to run firmware and software tests both in simulation and on real hardware that can be well adapted to FPGA-based accelerator electronics designs. We have built a test rack with a variety of hardware platforms. Relying on source code version control tools, when a developer submits a change to the code base, a multi-stage test pipeline is triggered. Unit tests are run automatically, bitstreams are generated for the various supported FPGA platforms and loaded onto the FPGAs in the rack, and tests are run on hardware. Reports are generated upon test completion and notifications are sent to the developers in case of failure.
	Slides TUAPP01 [9.740 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP01
About •	paper received ※ 07 October 2019 paper accepted ※ 20 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP02	Development of the MTCA.4 I/O Cards for SPring-8 Upgrade and New 3 GeV Light Source	linac, LLRF, cavity, timing	665
	T. Fukui, N. Hosoda RIKEN SPring-8 Center, Innovative Light Sources Division, Hyogo, Japan M. Ishii JASRI/SPring-8, Hyogo-ken, Japan E. Iwai, H. Maesaka, T. Ohshima RIKEN SPring-8 Center, Sayo-cho, Sayo-gun, Hyogo, Japan
	We will start a full energy injection from the SACLA to the SPring-8 from next year as a part of the SPring-8 upgrade. For this, we developed several I/O cards with the MTCA.4 form factor. One of the key issues is a timing synchronization between SACLA and SPring-8. We implemented required functions on the FPGA logic of a commercially available I/O card. We develop a module to distribute a trigger and clocks. We also developed cards used for the beam position monitor (BPM) and low-level RF system (LLRF). Those are included two types of cards. One is a 16-bit digitizer used for LLRF for the SPring-8 since 2018 march. We will use the card for the BPM with modified FPGA logic. Second is an implementation of functions with the pulsed RF signals processed on the FPGA logic of a commercially available card. These functions are used for the BPM of the beam transport line from the SACLA to SPring-8. The existing system is used 1 Hz beam repetition but we need more than 10 Hz to achieve an injection time less than 20 minutes to maximize user time. We will report the performance of the MTCA.4 cards, the upgrade plan of the SPring-8, and the construction of the 3 GeV Light Source.
	Slides TUAPP02 [7.123 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP02
About •	paper received ※ 01 October 2019 paper accepted ※ 20 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP03	Low-Cost Modular Platform for Custom Electronics in Radiation-Exposed and Radiation-Free Areas at CERN	radiation, controls, power-supply, Ethernet	671
	G. Daniluk, C. Gentsos, E. Gousiou, L. Patnaik, M. Rizzi CERN, Geneva, Switzerland
	The CERN control system is comprised of multiple layers of hardware and software. These tiers extend from the hardware deployed close to the machine, up to the software running on computers that operators use for control and monitoring. We are currently developing a new centrally supported service in the layers closest to the accelerator - Distributed I/O and Fieldbus. A key aspect of this project is the selection of industrial standards for the layers, which are currently dominated by custom, in-house designed solutions. Regarding the Distributed I/O layer, this paper describes how we are adapting CompactPCI Serial (CPCI-S) to be suitable as the low-cost modular hardware platform for remote analog and digital I/O applications in radiation-exposed as well as radiation-free areas. We are designing a low cost 3U chassis with a CPCI-S backplane accompanied by a radiation tolerant, switched-mode power supply and an FPGA-based System Board. Regarding the Fieldbus layer, the paper focuses on the radiation-tolerant implementation of the Industrial Ethernet protocol, Powerlink.
	Slides TUAPP03 [7.663 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP03
About •	paper received ※ 27 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP04	Extending the Life of the VME Infrastructure at BNL	controls, interface, Ethernet, hardware	678
	W.E. Pekrul, C. Theisen BNL, Upton, New York, USA
	A large installation of VME controllers have been used to control and monitor the RHIC Accelerator complex at BNL. As this equipment ages a number of upgrade options are being pursued. This paper describes an FPGA based VME controller board development being undertaken to provide a upgrade path for control applications that reuses existing racks and power supplies and a catalogue of custom application boards. This board is based on a Xilinx Zynq that includes an ARM-9 and a large FPGA fabric. The board includes DRAM, SPI-Flash, Ethernet, SD card, USB, SFP, FMC and an Artix FPGA to support the VME bus protocol. The first application of a magnet quench detector will also be described.
	Slides TUAPP04 [2.138 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP04
About •	paper received ※ 01 October 2019 paper accepted ※ 20 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP05	PandABlocks - a Flexible Framework for Zynq7000-Based SoC Configuration	hardware, framework, detector, controls	682
	G.B. Christian, M.G. Abbott, T.M. Cobb, C.A. Colborne, A.M. Cousins, P. Garrick, T.E. Trafford, I.S. Uzun DLS, Oxfordshire, United Kingdom Y.-M. Abiven, J. Bisou, F. Langlois, G. Renaud, G. Thibaux, S. Zhang SOLEIL, Gif-sur-Yvette, France S.M. Minolli NEXEYA Systems, La Couronne, France
	The PandABlocks framework comprises the FPGA logic, TCP server, webserver, boot sources and root filesystem, developed for the PandABox platform by Diamond Light Source and Synchrotron Soleil, for advanced beamline scanning applications. The PandABox platform uses a PicoZed System-on-Module, comprising a Zynq-7030 SoC, coupled to a carrier board containing removable position encoder modules, as well as various input and outputs. An FMC connector provides access to ADC/DACs or additional I/O, and gigabit transceivers on the Zynq allow communication with other systems via SFP modules. Specific functions and hardware resources are represented by functional blocks, which are run-time configurable and re-wireable courtesy of multiplexed data and control buses shared between all blocks. Recent changes to the PandABlocks framework are discussed which allow the auto-generation of the FPGA code and tcl automation scripts, using Python and the jinja2 templating engine, for any combination of functional blocks and SFP/FMC modules. The framework can target hardware platforms other than PandABox and could be deployed for other Zynq-based applications requiring on-the-fly reconfigurable logic.
	Slides TUAPP05 [5.484 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP05
About •	paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUCPL06	Accelerating Machine Learning for Machine Physics (an AMALEA-project at KIT)	controls, bunching, hardware, storage-ring	781
	T. Boltz, E. Bründermann, M. Caselle, A. Kopmann, W. Mexner, A.-S. Müller, W. Wang KIT, Karlsruhe, Germany
	The German Helmholtz Innovation Pool project will explore and provide novel cutting edge Machine Learning techniques to address some of the most urgent challenges in the era of large data harvests in accelerator physics. Progress in virtually all areas of accelerator based physics research relies on recording and analyzing enormous amounts of data. This data is produced by progressively sophisticated fast detectors alongside increasingly precise accelerator diagnostic systems. As KIT contribution to AMALEA it is planned to investigate a design of a fast and adaptive feedback system that reacts to small changes in the charge distribution of the electron bunch and establishes extensive control over the longitudinal beam dynamics. As a promising and well-motivated approach, reinforcement learning methods are considered. In a second step the algorithm will be implemented as a pilot experiment to a novel PCIe FPGA readout electronics card based on Zynq UltraScale⁺ MultiProcessor System on-Chip (MPSoC).
	Slides TUCPL06 [5.955 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUCPL06
About •	paper received ※ 27 September 2019 paper accepted ※ 01 November 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEMPL002	Project Nheengatu: EPICS support for CompactRIO FPGA and LabVIEW-RT	EPICS, LabView, controls, software	997
	D. Alnajjar, G.S. Fedel, J.R. Piton LNLS, Campinas, Brazil
	A novel solution for integrating EPICS with Compact RIO (cRIO), the real-time embedded industrial controllers by National Instruments (NI), is proposed under the name Nheengatu (NHE). The cRIO controller, which is equipped with a processor running a real-time version of Linux (LinuxRT) and a Xilinx Kintex FPGA, is extremely powerful for control systems since it can be used to program real-time complex data processing and fine control tasks on both the LinuxRT and the FPGA. The proposed solution enables the control and monitoring of all tasks running on LinuxRT and the FPGA through EPICS. The devised solution is not limited to any type of cRIO module. Its architecture can be abstracted into four groups: FPGA and LabVIEW-RT interface blocks, the Nheengatu library, Device Support and IOC. The Nheengatu library, device support and IOC are generic - they are compiled only once and can be deployed on all cRIOs available. Consequently, a setup-specific configuration file is provided to the IOC upon instantiation. The configuration file contains all data for the devised architecture to configure the FPGA and to enable communication between EPICS and the FPGA/LabVIEW-RT interface blocks.
	Poster WEMPL002 [0.565 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEMPL002
About •	paper received ※ 14 September 2019 paper accepted ※ 02 October 2020 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEMPR009	Development of Event Receiver on Zynq-7000 Evaluation Board	timing, controls, distributed, linac	1063
	H. Sugimura KEK, Ibaraki, Japan
	The timing system of SuperKEKB accelerator is used Event Timing System developed by Micro Research Finland. In this presentation, we tested the receiver on Zynq7000 evaluation board. The serialized event data are transferred from Event Generator to Event Receiver by using GTX transceiver. So, we selected Zynq7000(7z030) as receiver, because the FPGA has the GTX. And also, Zynq is mounted on arm processor, it is easily able to control received event data stream by using EPICS ICO. Finally we are aiming to combine event system and RF or BPM system in one FPGA board.
	Poster WEMPR009 [0.572 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEMPR009
About •	paper received ※ 17 September 2019 paper accepted ※ 09 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA010	Control Systems Design for LCLS-II Fast Wire Scanners at SLAC National Accelerator Laboratory	controls, EPICS, software, feedback	1075
	N. Balakrishnan, H. Bassan, J.D. Bong, M.L. Campell, P. Krejcik, K.R. Lauer, J.J. Olsen, L. Sapozhnikov SLAC, Menlo Park, California, USA
	One of the primary diagnostic tools for beam emittance measurement at the Linac Coherent Light Source II (LCLS-II), an upgrade of the SLAC National Accelerator Laboratory’s Linac Coherent Light Source (LCLS) facility, is the wire scanners. LCLS-II’s new Fast Wire Scanner (FWS) is based on a similar mechanical design of linear servo motor with position feedback from an incremental encoder as that for LCLS. With a high repetition rate of up to 1 MHz from the superconducting accelerator of LCLS-II, it is no longer sufficient to use point-to-point EPICS-controlled moves from wire to wire, as continued exposure will damage the wires. The system needs to perform on-the-fly scans, with a single position versus time profile calculated in advance and executed in a single coordinated motion by Aerotech Ensemble motion controller. The new fast wire scanner control system has several advantages over LCLS fast wire scanner controls with the capability to program safety features directly on the drive and integrate machine protection checks on an FPGA. This paper will focus on the software architecture and implementation for LCLS-II Fast Wire Scanners.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA010
About •	paper received ※ 30 September 2019 paper accepted ※ 11 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA016	A/D and D/A Processing Unit for Real Time Control of Suspended Masses in Advanced Virgo Interferometer	controls, electronics, electron, detector	1098
	M. Bitossi, A. Gennai INFN-Pisa, Pisa, Italy D. Passuello University of Pisa and INFN, Pisa, Italy
	AdV* is the project to upgrade the VIRGO* interferometric detector of gravitational waves. We present a major upgrade consisting of the design of new control electronics of the seismic isolation systems called Super-Attenuators (SAs). SAs are mechanical structures used to insulate optical elements from seismic noise. The control electronics are used to manage sensors, actuators, and stepping motors placed in the SAs. The design effort resulted in a high-performance signal conditioning and processing platform (UDSPT) that enables users to implement hard real-time control systems. The form factor is a variation of a double compact Module PICMG AMC.0 R2.0 Advanced MC. The key features are a TI DSP embedded, two GE ports, an AMC Interface containing SRIO, and GE, an FPGA interfacing data converters through PCIe. Additionally, it includes six 24-bit 3.83 MHz ADC and six 24-bit 320 kHz DAC converters, with fully differential inputs and outputs. In a single local control unit - a single 6U x 19 crate - up to 72 ADC + 72 DAC channels supported by 720 GFLOPs are allocated. A total of 20 local control units have been installed and currently are controlling ten SAs in the AdV detector. AdV Tech Des Rep 13 April 2012. Advanced Virgo Baseline Design *J. Phys.: Conf. Ser., 203(2010)012074.
	Poster WEPHA016 [1.858 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA016
About •	paper received ※ 23 September 2019 paper accepted ※ 11 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA023	Co-Simulation of HDL Using Python and MATLAB Over Tcl TCP/IP Socket in Xilinx Vivado and Modelsim Tools	simulation, controls, interface, MMI	1127
	Ł. Butkowski, B. Dursun, C. Gümüş, M.K. Karakurt DESY, Hamburg, Germany
	This paper presents the solution, which helps in the simulation and verification of the implementation of the Digital Signal Processing (DSP) algorithms written in hardware description language (HDL). Many vendor tools such as Xilinx ISE/Vivado or Mentor Graphics ModelSim are using Tcl as an application programming interface. The main idea of the co-simulation is to use the Tcl TCP/IP socket, which is Tcl build in feature, as the interface to the simulation tool. Over this interface the simulation is driven by the external tool. The stimulus vectors as well as the model and verification are implemented in Python or MATLAB and the data with simulator is exchanged over dedicated protocol. The tool, which was called cosimtcp, was developed in Deutsches Elektronen-Synchrotron (DESY). The tool is a set of scripts that provide a set of functions. This tool has been successfully used to verify many DSP algorithms implemented in the FPGA chips of the Low Level Radio Frequency (LLRF) and synchronization systems of the European X-Ray Free Electron Laser (E-XFEL) accelerator. Cosimtcp is an open source available tool.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA023
About •	paper received ※ 30 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA027	Evaluation of Timing and Synchronization Techniques on NI CompactRIO Platforms	controls, network, timing, hardware	1141
	O.Ø. Andreassen, C. Charrondière, K. Develle, R.E. Rossel, T. Zilliox CERN, Geneva, Switzerland
	For distributed data acquisition and control system, clock synchronization between devices is key. The internal CPU clock of a CompactRIO has an accuracy of 40 ppm at 25 degree Celsius, which can cause up to 3 sec of drift per day. To compensate for this drift, common practice is to use a central clock (such as NTP) to synchronize the systems. In addition, the cRIO has an onboard FPGA which has its own 40 MHz clock. This clock is not synchronized with the CPU, and will also cause time drift. For short measurements, this drift is usually negligible, but for continuous data acquisition systems, running 24/7, the accumulated error has to be compensated. This article will show how we synchronized all clocks across multiple systems used for monitoring seismic activities in the LHC underground and surface areas. It will also describe the mechanism used to cross check synchronization by using the CERN developed White Rabbit timing system.
	Poster WEPHA027 [0.567 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA027
About •	paper received ※ 26 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA035	Firmware Layer Implementation of the nBLM and icBLM Systems for ESS Project	linac, neutron, interface, simulation	1157
	W. Cichalewski, G.W. Jabłoński, W. Jałmużna, R. Kiełbik TUL-DMCS, Łódź, Poland F.S. Alves, H. Carling, I. Dolenc Kittelmann, S. Farina, K.E. Rosengren, T.J. Shea ESS, Lund, Sweden
	Funding: Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2018/02 Both ionization chamber Beam Loss Monitor (icBLM) and neutron Beam Loss Monitor (nBLM) systems are fundamental components of European Spallation Source (ESS) accelerator safety systems. Main responsibility of this system is instantaneous and reliable detection of accelerated proton beam loss that exceeds predefined safety threshold. Nowadays DMCS (as an in-kind partner to ESS) is responsible for beam loss detection algorithm implementation, evaluation and deployment in firmware. As a hardware platform for mentioned systems MTCA.4 based form factor electronic components have been chosen (delivered by IOXOS). This contribution focuses on both cases (nBLM and icBLM) firmware realisation presentation. Proposed and developed firmware structure and functional blocks that fulfills specified by ESS requirements are described. Additionally, some aspects of the system FPGA circuit resource usage and achieved performance is being discussed.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA035
About •	paper received ※ 01 October 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA042	Commissioning of the 352 MHz Transverse Feedback System at the Advance Photon Source	feedback, controls, operation, storage-ring	1180
	N.P. DiMonte, C. Yao ANL, Lemont, Illinois, USA
	Funding: Work supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357. With the success and reliability of the transverse feedback system installed at the Advance Photon Source (APS), an upgraded version to this system was commissioned in 2019. The previous system operated at a third of the storage-ring bunch capacity, or 432 of the available 1296 bunches. This upgrade samples all 1296 bunches which allowed corrections to be made on any selected bunch in a single storage-ring turn. To facilitate this upgrade the development of a new analog I/O board capable of 352 MHz operation was necessary. This paper discusses some of the challenges associated in processing one bunch out of 1296 bunches and how flexible the system can be in processing all 1296 bunches. We will also report on the performance of this system.
	Poster WEPHA042 [10.931 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA042
About •	paper received ※ 24 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA103	Backward Compatible Update of the Timing System of WEST	network, timing, distributed, controls	1338
	Y. Moudden, A. Barbuti, G. Caulier, T. Poirier, B. Santraine, B. Vincent CEA/DRF/IRFM, St Paul Lez Durance, France
	Between 2013 and 2016, the tokamak Tore Supra in operation at Cadarache (CEA-France) since 1988 underwent a major upgrade following which it was renamed WEST (Tungsten [W] Environment in Steady state Tokamak). The synchronization system however was not upgraded since 1999. At the time, a robust design was achieved based on AMD’s TAXI chip: clock and events are distributed from a central emitter over a star shaped network of simplex optical links to electronic crates around the tokamak. Unfortunately, spare boards were not produced in sufficient quantities and the TAXI is obsolete. In fact, multigigabit serial communication standards question the future availability of any such low rate SerDeses. Designing replacement boards provides an opportunity for a new CDR solution and extended functionalities (loss-of-lock detection, latency monitoring). Backward compatibility is a major constraint given the lack of resources for a full upgrade. We will first describe the current state of the timing network of WEST, then the implementation of a custom CDR in full firmware, using the IOSerDeses of Xilinx FPGAs and will finally provide preliminary results on development boards. "Upgrade of the timing system for Tore Supra long pulses", D. Moulin et al. IEEE RealTime Conference 1999 **http://hep.uchicago.edu/~thliu/projects/Pulsar/other_doc/TAXIchip.pdf
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA103
About •	paper received ※ 30 September 2019 paper accepted ※ 03 October 2020 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA151	A Very Lightweight Process Variable Server	controls, GUI, software, monitoring	1449
	A. Sukhanov, J.P. Jamilkowski BNL, Upton, New York, USA
	Funding: Work supported by Brookhaven Science Associates, LLC under Contract No. DE-SC0012704 with the U.S. Department of Energy. Modern instruments are often supplied with rich proprietary software tools, which makes it difficult to integrate them to an existing control systems. The liteServer is very lightweight, low latency, cross-platform network protocol for signal monitoring and control. It provides very basic functionality of popular channel access protocols like CA or pvAccess of EPICS. It supports request-reply patterns: ’info’, ’get’ and ’set’ requests and publish-subscribe pattern: ’monitor’ request. The main scope of the liteServer is: 1) provide control and monitoring for instruments supplied with proprietary software, 2) provide fastest possible Ethernet transactions, 3) make it possible to implement in FPGA without CPU core. The transport protocol is connection-less (UDP) and data serialization format is Universal Binary JSON (UBJSON). The UBJSON provides complete compatibility with the JSON specification, it is very efficient and fast. A liteServer-based system can be connected to existing control system using simple bridge program (bridges for EPICS and RHIC Ado are provided).
	Poster WEPHA151 [0.383 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA151
About •	paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THCPR01	Novel FPGA-Based Instrumentation for Personnel Safety Systems in Particle Accelerator Facility	hardware, radiation, software, controls	1617
	S. Pioli, M. Belli, M.M. Beretta, B. Buonomo, P. Ciambrone, D.G.C. Di Giulio, L.G. Foggetta, O. Frasciello, A. Variola INFN/LNF, Frascati, Italy P. Valente INFN-Roma, Roma, Italy
	Personnel safety system for particle accelerator facility involves different devices to monitor gates, shielding doors, dosimetry stations, search and emergency buttons. In order to achieve the proper reliability, these systems are developed compliant with functional safety standards involving stable technologies like relays and, recently, PLC. This work will report benchmark of a new FPGA-based system, developed at INFN-LNF, from the design to the validation phase of the prototype currently operating inside the linac bunker of Dafne. In order to achieve the compliance with functional safety standard (IEC-61508), NCRP report 88 on "Radiation Alarms and Access Control Systems" and ANSI report 43 on "Radiation Safety for the Design and Operation of Particle Accelerator", this novel instrument has been designed capable of: devices monitoring in real-time, dual modular redundancy, fail-safe, fool-proof and multi-node architecture on optical link. The aim of this project is to illustrate the feasibility of FPGA technology in the field of personnel safety and develop a standard solution for other fields like the machine protection.
	Slides THCPR01 [2.928 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR01
About •	paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THCPR03	A Safety Rated FPGA Framework for Fast Safety Systems	PLC, electron, hardware, diagnostics	1626
	F. Tao, B.M. Bennett, D.G. Brown, J. Jones, M.W. Stettler SLAC, Menlo Park, California, USA
	In this paper, we will introduce a generic safety-rated FPGA design template. FMEDA analysis, hardware reliability modeling, firmware development, verification and validation will be described in details to demonstrate the IEC 61508 compliant development process. In this dual redundant design, each chain consists a FPGA chip from different manufacturers to minimize the potential common cause failures. Cross checks between FPGAs and end-to-end self-checks are performed to increase the diagnostic coverage and improve the reliability. Based on this safety FPGA template, an Average Current Monitor (ACM) system is developed at SLAC with the addition of a safety PLC for diagnostics and a HMI for user interface. The overall system is deployed as part of Beam Containment System (BCS) to limit the beam current with the target Safety Integrity Level (SIL) 2.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR03
About •	paper received ※ 01 October 2019 paper accepted ※ 08 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Other Keywords

Page

MOPHA049

Test-bench Design for New Beam Instrumentation Electronics at CERN

instrumentation, hardware, electron, electronics

323

M. Gonzalez-Berges, J.O. Robinson, M. Saccani, V. Schramm, M.A. Stachon
CERN, Meyrin, Switzerland

The Beam Instrumentation group has designed a new general-purpose VME acquisition board that will serve as the basis for the design of new instruments and will be used in the renovation of existing systems in the future. Around 1200 boards have been produced. They underwent validation, environmental stress screening and run-in tests to ensure their performance and long term reliability. This allowed to identify potential issues at an early stage and mitigate them, minimizing future interventions and downtime. A dedicated test-bench was designed to drive the tests and continuously monitor the board functionality. One board has more than 45 functions including memories, high speed serial links and a variety of diagnostics. The test-bench was fully integrated with the CERN asset management system to allow lifecycle management from the initial production phase. The data captured during these tests was stored and analyzed regularly to find sources of failures. This was the first time that such a complete test-bench has been used. This paper presents all the details of the test-bench design and implementation.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA049

About •

paper received ※ 30 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA076

Timing System Upgrade for Medical Linear Accelerator Project at SLRI

timing, hardware, GUI, electron

392

R. Rujanakraikarn, P. Koonpong, S. Tesprasitte
SLRI, Nakhon Ratchasima, Thailand

A prototype of 6 MeV medical linear accelerator has been under development at Synchrotron Light Research Institute (SLRI). Several subsystems of the machine have been carefully designed and tested to prepare for x-ray generation. To maintain proper operation of the machine, pulse signals are generated to synchronize various subsystems. The timing system, based on the previous version designed on Xilinx Spartan-3 FPGA, is upgraded with better timing resolution, easier configuration with more timing channels, and future expansion of the system. A new LabVIEW GUI is also designed with more details on timing parameters for easy customization. The result of this new design is satisfactorily achieved with the resolution of 10 nanoseconds per time step and up to 15 synchronized timing channels implemented on two FPGA modules.

Poster MOPHA076 [0.727 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA076

About •

paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA137

Timing Synchronization and Controls Integration for ESS Detector Readout

detector, EPICS, controls, timing

547

W. Smith
STFC/DL, Daresbury, Warrington, Cheshire, United Kingdom
S. Alcock, J.M.C. Nilsson
ESS, Lund, Sweden

The European Spallation Source (ESS) is a new facility being built in Lund, Sweden, which when finished will be the world’s most powerful neutron source. STFC has an in-kind project with the Detector group at ESS to provide timing and control systems integration for the detector data readout system. This paper describes how time is synchronised and distributed to the readout system from the ESS timing system, and how EPICS is used to implement a controls interface exposing the functionality of detector front ends.

Poster MOPHA137 [1.180 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA137

About •

paper received ※ 30 September 2019 paper accepted ※ 09 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA152

Use of Multi-Network Fieldbus for Integration of Low-Level Intelligent Controller Within Control Architecture of Fast Pulsed System at CERN

controls, network, interface, Ethernet

589

N. Voumard, C. Boucly, M.P. Pimentel, L. Strobino, P. Van Trappen
CERN, Geneva, Switzerland

Fieldbuses and Industrial Ethernet networks are extensively used for the control of fast-pulsed magnets at CERN. With the ongoing trend to develop increasingly more complex low-level intelligent controllers near to the actuators and sensors, the flexibility to integrate these within different control architectures grows in importance. In order to reduce development efforts and keep the fieldbus choice open, a multi-network field-bus technology has been selected for the network interfacing part of the controllers. Such an approach has been successfully implemented for several projects such as the development of high voltage capacitor chargers/dischargers, the surveillance of floating solid-state switch and the monitoring of a power triggering system that, today, are interfaced either to PROFIBUS-DP or PROFINET networks. The integration of various fieldbus interfaces within the controller and the required embedded software/gateware to manage to network communication are presented. The gain in flexibility, modularity and openness obtained through this approach is also reviewed.

Poster MOPHA152 [0.587 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA152

About •

paper received ※ 27 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA153

SoC Technology for Embedded Control and Interlocking Within Fast Pulsed Systems at CERN

controls, software, hardware, real-time

592

P. Van Trappen, E. Carlier, M. Gauthier, N. Magnin, E.J. Oltedal, J. Schipper
CERN, Geneva, Switzerland

The control of pulsed systems at CERN requires often the use of fast digital electronics to perform tight timing control and fast protection of high-voltage pulsed generators. For the implementation of such functionalities, a FPGA is the perfect candidate for the digital logic, however with limited integration potential within the control system. The market push for integrated devices, so called System on a Chip (SoC) - a tightly coupled ARM processing system and specific programmable logic in a single device, has allowed a better integration of the various components required for the control of pulsed systems. This technology is used for the implementation of fast switch interlocking logic, integrated within the CERN control framework by using embedded Linux running a Snap7 server. It is also used for the implementation of a lower-tier communication bridge between a front-end computer and a high fan-out multiplexing programmable logic for timing and analogue low-level control. This paper presents these two projects where the SoC technology has been deployed and discusses possible further applications within distributed real-time control architecture for distributed pulsed systems.

Poster MOPHA153 [0.828 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA153

About •

paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOPHA156

The Linux Device Driver Framework for High-Throughput Lossless Data Streaming Applications

Linux, software, interface, neutron

602

K. Vodopivec, J.E. Breeding
ORNL, Oak Ridge, Tennessee, USA
J.W. Sinclair
ORNL RAD, Oak Ridge, Tennessee, USA

Funding: This work was supported by the U.S. Department of Energy under contract DE-AC0500OR22725.
Many applications in experimental physics facilities require custom hardware solutions to control process parameters or to acquire data at high rates with high integrity. These hardware solutions typically require custom software implementations. The neutron scattering detectors at the Spallation Neutron Source at ORNL* implement custom protocols over optical fiber connected to a PCI express based read-out board. A dedicated kernel device driver provides an interface to the software application and must be able to sustain data bursts from a pulsed source while acquiring data for long periods of time. The same optical channel is also used as low-latency communication link to detector electronics for configuration and real time fault detection. This paper presents a Linux device driver design, implementation challenges in a low-latency high-throughput setup, real use case benchmarks and importance of clean application programming interface for seamless integration in control systems. This software implementation was developed as a generic framework and has been extended beyond neutron data acquisition. It is suitable to diverse applications where it allows for rapid FPGA development.
*Oak Ridge National Laboratory

Poster MOPHA156 [4.163 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA156

About •

paper received ※ 02 October 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP01

Hardware-in-the-Loop Testing of Accelerator Firmware

software, hardware, controls, LLRF

659

C. Serrano, M. Betz, L.R. Doolittle, S. Paiagua, V.K. Vytla
LBNL, Berkeley, California, USA

Continuous Integration (CI) is widely used in industry, especially in the software world. Here we propose a combination of CI processes to run firmware and software tests both in simulation and on real hardware that can be well adapted to FPGA-based accelerator electronics designs. We have built a test rack with a variety of hardware platforms. Relying on source code version control tools, when a developer submits a change to the code base, a multi-stage test pipeline is triggered. Unit tests are run automatically, bitstreams are generated for the various supported FPGA platforms and loaded onto the FPGAs in the rack, and tests are run on hardware. Reports are generated upon test completion and notifications are sent to the developers in case of failure.

Slides TUAPP01 [9.740 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP01

About •

paper received ※ 07 October 2019 paper accepted ※ 20 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP02

Development of the MTCA.4 I/O Cards for SPring-8 Upgrade and New 3 GeV Light Source

linac, LLRF, cavity, timing

665

T. Fukui, N. Hosoda
RIKEN SPring-8 Center, Innovative Light Sources Division, Hyogo, Japan
M. Ishii
JASRI/SPring-8, Hyogo-ken, Japan
E. Iwai, H. Maesaka, T. Ohshima
RIKEN SPring-8 Center, Sayo-cho, Sayo-gun, Hyogo, Japan

We will start a full energy injection from the SACLA to the SPring-8 from next year as a part of the SPring-8 upgrade. For this, we developed several I/O cards with the MTCA.4 form factor. One of the key issues is a timing synchronization between SACLA and SPring-8. We implemented required functions on the FPGA logic of a commercially available I/O card. We develop a module to distribute a trigger and clocks. We also developed cards used for the beam position monitor (BPM) and low-level RF system (LLRF). Those are included two types of cards. One is a 16-bit digitizer used for LLRF for the SPring-8 since 2018 march. We will use the card for the BPM with modified FPGA logic. Second is an implementation of functions with the pulsed RF signals processed on the FPGA logic of a commercially available card. These functions are used for the BPM of the beam transport line from the SACLA to SPring-8. The existing system is used 1 Hz beam repetition but we need more than 10 Hz to achieve an injection time less than 20 minutes to maximize user time. We will report the performance of the MTCA.4 cards, the upgrade plan of the SPring-8, and the construction of the 3 GeV Light Source.

Slides TUAPP02 [7.123 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP02

About •

paper received ※ 01 October 2019 paper accepted ※ 20 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP03

Low-Cost Modular Platform for Custom Electronics in Radiation-Exposed and Radiation-Free Areas at CERN

radiation, controls, power-supply, Ethernet

671

G. Daniluk, C. Gentsos, E. Gousiou, L. Patnaik, M. Rizzi
CERN, Geneva, Switzerland

The CERN control system is comprised of multiple layers of hardware and software. These tiers extend from the hardware deployed close to the machine, up to the software running on computers that operators use for control and monitoring. We are currently developing a new centrally supported service in the layers closest to the accelerator - Distributed I/O and Fieldbus. A key aspect of this project is the selection of industrial standards for the layers, which are currently dominated by custom, in-house designed solutions. Regarding the Distributed I/O layer, this paper describes how we are adapting CompactPCI Serial (CPCI-S) to be suitable as the low-cost modular hardware platform for remote analog and digital I/O applications in radiation-exposed as well as radiation-free areas. We are designing a low cost 3U chassis with a CPCI-S backplane accompanied by a radiation tolerant, switched-mode power supply and an FPGA-based System Board. Regarding the Fieldbus layer, the paper focuses on the radiation-tolerant implementation of the Industrial Ethernet protocol, Powerlink.

Slides TUAPP03 [7.663 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP03

About •

paper received ※ 27 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP04

Extending the Life of the VME Infrastructure at BNL

controls, interface, Ethernet, hardware

678

W.E. Pekrul, C. Theisen
BNL, Upton, New York, USA

A large installation of VME controllers have been used to control and monitor the RHIC Accelerator complex at BNL. As this equipment ages a number of upgrade options are being pursued. This paper describes an FPGA based VME controller board development being undertaken to provide a upgrade path for control applications that reuses existing racks and power supplies and a catalogue of custom application boards. This board is based on a Xilinx Zynq that includes an ARM-9 and a large FPGA fabric. The board includes DRAM, SPI-Flash, Ethernet, SD card, USB, SFP, FMC and an Artix FPGA to support the VME bus protocol. The first application of a magnet quench detector will also be described.

Slides TUAPP04 [2.138 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP04

About •

paper received ※ 01 October 2019 paper accepted ※ 20 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUAPP05

PandABlocks - a Flexible Framework for Zynq7000-Based SoC Configuration

hardware, framework, detector, controls

682

G.B. Christian, M.G. Abbott, T.M. Cobb, C.A. Colborne, A.M. Cousins, P. Garrick, T.E. Trafford, I.S. Uzun
DLS, Oxfordshire, United Kingdom
Y.-M. Abiven, J. Bisou, F. Langlois, G. Renaud, G. Thibaux, S. Zhang
SOLEIL, Gif-sur-Yvette, France
S.M. Minolli
NEXEYA Systems, La Couronne, France

The PandABlocks framework comprises the FPGA logic, TCP server, webserver, boot sources and root filesystem, developed for the PandABox platform by Diamond Light Source and Synchrotron Soleil, for advanced beamline scanning applications. The PandABox platform uses a PicoZed System-on-Module, comprising a Zynq-7030 SoC, coupled to a carrier board containing removable position encoder modules, as well as various input and outputs. An FMC connector provides access to ADC/DACs or additional I/O, and gigabit transceivers on the Zynq allow communication with other systems via SFP modules. Specific functions and hardware resources are represented by functional blocks, which are run-time configurable and re-wireable courtesy of multiplexed data and control buses shared between all blocks. Recent changes to the PandABlocks framework are discussed which allow the auto-generation of the FPGA code and tcl automation scripts, using Python and the jinja2 templating engine, for any combination of functional blocks and SFP/FMC modules. The framework can target hardware platforms other than PandABox and could be deployed for other Zynq-based applications requiring on-the-fly reconfigurable logic.

Slides TUAPP05 [5.484 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUAPP05

About •

paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

TUCPL06

Accelerating Machine Learning for Machine Physics (an AMALEA-project at KIT)

controls, bunching, hardware, storage-ring

781

T. Boltz, E. Bründermann, M. Caselle, A. Kopmann, W. Mexner, A.-S. Müller, W. Wang
KIT, Karlsruhe, Germany

The German Helmholtz Innovation Pool project will explore and provide novel cutting edge Machine Learning techniques to address some of the most urgent challenges in the era of large data harvests in accelerator physics. Progress in virtually all areas of accelerator based physics research relies on recording and analyzing enormous amounts of data. This data is produced by progressively sophisticated fast detectors alongside increasingly precise accelerator diagnostic systems. As KIT contribution to AMALEA it is planned to investigate a design of a fast and adaptive feedback system that reacts to small changes in the charge distribution of the electron bunch and establishes extensive control over the longitudinal beam dynamics. As a promising and well-motivated approach, reinforcement learning methods are considered. In a second step the algorithm will be implemented as a pilot experiment to a novel PCIe FPGA readout electronics card based on Zynq UltraScale⁺ MultiProcessor System on-Chip (MPSoC).

Slides TUCPL06 [5.955 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-TUCPL06

About •

paper received ※ 27 September 2019 paper accepted ※ 01 November 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEMPL002

Project Nheengatu: EPICS support for CompactRIO FPGA and LabVIEW-RT

EPICS, LabView, controls, software

997

D. Alnajjar, G.S. Fedel, J.R. Piton
LNLS, Campinas, Brazil

A novel solution for integrating EPICS with Compact RIO (cRIO), the real-time embedded industrial controllers by National Instruments (NI), is proposed under the name Nheengatu (NHE). The cRIO controller, which is equipped with a processor running a real-time version of Linux (LinuxRT) and a Xilinx Kintex FPGA, is extremely powerful for control systems since it can be used to program real-time complex data processing and fine control tasks on both the LinuxRT and the FPGA. The proposed solution enables the control and monitoring of all tasks running on LinuxRT and the FPGA through EPICS. The devised solution is not limited to any type of cRIO module. Its architecture can be abstracted into four groups: FPGA and LabVIEW-RT interface blocks, the Nheengatu library, Device Support and IOC. The Nheengatu library, device support and IOC are generic - they are compiled only once and can be deployed on all cRIOs available. Consequently, a setup-specific configuration file is provided to the IOC upon instantiation. The configuration file contains all data for the devised architecture to configure the FPGA and to enable communication between EPICS and the FPGA/LabVIEW-RT interface blocks.

Poster WEMPL002 [0.565 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEMPL002

About •

paper received ※ 14 September 2019 paper accepted ※ 02 October 2020 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEMPR009

Development of Event Receiver on Zynq-7000 Evaluation Board

timing, controls, distributed, linac

1063

H. Sugimura
KEK, Ibaraki, Japan

The timing system of SuperKEKB accelerator is used Event Timing System developed by Micro Research Finland. In this presentation, we tested the receiver on Zynq7000 evaluation board. The serialized event data are transferred from Event Generator to Event Receiver by using GTX transceiver. So, we selected Zynq7000(7z030) as receiver, because the FPGA has the GTX. And also, Zynq is mounted on arm processor, it is easily able to control received event data stream by using EPICS ICO. Finally we are aiming to combine event system and RF or BPM system in one FPGA board.

Poster WEMPR009 [0.572 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEMPR009

About •

paper received ※ 17 September 2019 paper accepted ※ 09 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA010

Control Systems Design for LCLS-II Fast Wire Scanners at SLAC National Accelerator Laboratory

controls, EPICS, software, feedback

1075

N. Balakrishnan, H. Bassan, J.D. Bong, M.L. Campell, P. Krejcik, K.R. Lauer, J.J. Olsen, L. Sapozhnikov
SLAC, Menlo Park, California, USA

One of the primary diagnostic tools for beam emittance measurement at the Linac Coherent Light Source II (LCLS-II), an upgrade of the SLAC National Accelerator Laboratory’s Linac Coherent Light Source (LCLS) facility, is the wire scanners. LCLS-II’s new Fast Wire Scanner (FWS) is based on a similar mechanical design of linear servo motor with position feedback from an incremental encoder as that for LCLS. With a high repetition rate of up to 1 MHz from the superconducting accelerator of LCLS-II, it is no longer sufficient to use point-to-point EPICS-controlled moves from wire to wire, as continued exposure will damage the wires. The system needs to perform on-the-fly scans, with a single position versus time profile calculated in advance and executed in a single coordinated motion by Aerotech Ensemble motion controller. The new fast wire scanner control system has several advantages over LCLS fast wire scanner controls with the capability to program safety features directly on the drive and integrate machine protection checks on an FPGA. This paper will focus on the software architecture and implementation for LCLS-II Fast Wire Scanners.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA010

About •

paper received ※ 30 September 2019 paper accepted ※ 11 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA016

A/D and D/A Processing Unit for Real Time Control of Suspended Masses in Advanced Virgo Interferometer

controls, electronics, electron, detector

1098

M. Bitossi, A. Gennai
INFN-Pisa, Pisa, Italy
D. Passuello
University of Pisa and INFN, Pisa, Italy

AdV* is the project to upgrade** the VIRGO*** interferometric detector of gravitational waves. We present a major upgrade consisting of the design of new control electronics of the seismic isolation systems called Super-Attenuators (SAs)*. SAs are mechanical structures used to insulate optical elements from seismic noise. The control electronics are used to manage sensors, actuators, and stepping motors placed in the SAs. The design effort resulted in a high-performance signal conditioning and processing platform (UDSPT) that enables users to implement hard real-time control systems. The form factor is a variation of a double compact Module PICMG AMC.0 R2.0 Advanced MC. The key features are a TI DSP embedded, two GE ports, an AMC Interface containing SRIO, and GE, an FPGA interfacing data converters through PCIe. Additionally, it includes six 24-bit 3.83 MHz ADC and six 24-bit 320 kHz DAC converters, with fully differential inputs and outputs. In a single local control unit - a single 6U x 19 crate - up to 72 ADC + 72 DAC channels supported by 720 GFLOPs are allocated. A total of 20 local control units have been installed and currently are controlling ten SAs in the AdV detector.
*AdV Tech Des Rep 13 April 2012.
**Advanced Virgo Baseline Design
***J. Phys.: Conf. Ser., 203(2010)012074.

Poster WEPHA016 [1.858 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA016

About •

paper received ※ 23 September 2019 paper accepted ※ 11 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA023

Co-Simulation of HDL Using Python and MATLAB Over Tcl TCP/IP Socket in Xilinx Vivado and Modelsim Tools

simulation, controls, interface, MMI

1127

Ł. Butkowski, B. Dursun, C. Gümüş, M.K. Karakurt
DESY, Hamburg, Germany

This paper presents the solution, which helps in the simulation and verification of the implementation of the Digital Signal Processing (DSP) algorithms written in hardware description language (HDL). Many vendor tools such as Xilinx ISE/Vivado or Mentor Graphics ModelSim are using Tcl as an application programming interface. The main idea of the co-simulation is to use the Tcl TCP/IP socket, which is Tcl build in feature, as the interface to the simulation tool. Over this interface the simulation is driven by the external tool. The stimulus vectors as well as the model and verification are implemented in Python or MATLAB and the data with simulator is exchanged over dedicated protocol. The tool, which was called cosimtcp, was developed in Deutsches Elektronen-Synchrotron (DESY). The tool is a set of scripts that provide a set of functions. This tool has been successfully used to verify many DSP algorithms implemented in the FPGA chips of the Low Level Radio Frequency (LLRF) and synchronization systems of the European X-Ray Free Electron Laser (E-XFEL) accelerator. Cosimtcp is an open source available tool.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA023

About •

paper received ※ 30 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA027

Evaluation of Timing and Synchronization Techniques on NI CompactRIO Platforms

controls, network, timing, hardware

1141

O.Ø. Andreassen, C. Charrondière, K. Develle, R.E. Rossel, T. Zilliox
CERN, Geneva, Switzerland

For distributed data acquisition and control system, clock synchronization between devices is key. The internal CPU clock of a CompactRIO has an accuracy of 40 ppm at 25 degree Celsius, which can cause up to 3 sec of drift per day. To compensate for this drift, common practice is to use a central clock (such as NTP) to synchronize the systems. In addition, the cRIO has an onboard FPGA which has its own 40 MHz clock. This clock is not synchronized with the CPU, and will also cause time drift. For short measurements, this drift is usually negligible, but for continuous data acquisition systems, running 24/7, the accumulated error has to be compensated. This article will show how we synchronized all clocks across multiple systems used for monitoring seismic activities in the LHC underground and surface areas. It will also describe the mechanism used to cross check synchronization by using the CERN developed White Rabbit timing system.

Poster WEPHA027 [0.567 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA027

About •

paper received ※ 26 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA035

Firmware Layer Implementation of the nBLM and icBLM Systems for ESS Project

linac, neutron, interface, simulation

1157

W. Cichalewski, G.W. Jabłoński, W. Jałmużna, R. Kiełbik
TUL-DMCS, Łódź, Poland
F.S. Alves, H. Carling, I. Dolenc Kittelmann, S. Farina, K.E. Rosengren, T.J. Shea
ESS, Lund, Sweden

Funding: Work supported by Polish Ministry of Science and Higher Education, decision number DIR/WK/2018/02
Both ionization chamber Beam Loss Monitor (icBLM) and neutron Beam Loss Monitor (nBLM) systems are fundamental components of European Spallation Source (ESS) accelerator safety systems. Main responsibility of this system is instantaneous and reliable detection of accelerated proton beam loss that exceeds predefined safety threshold. Nowadays DMCS (as an in-kind partner to ESS) is responsible for beam loss detection algorithm implementation, evaluation and deployment in firmware. As a hardware platform for mentioned systems MTCA.4 based form factor electronic components have been chosen (delivered by IOXOS). This contribution focuses on both cases (nBLM and icBLM) firmware realisation presentation. Proposed and developed firmware structure and functional blocks that fulfills specified by ESS requirements are described. Additionally, some aspects of the system FPGA circuit resource usage and achieved performance is being discussed.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA035

About •

paper received ※ 01 October 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA042

Commissioning of the 352 MHz Transverse Feedback System at the Advance Photon Source

feedback, controls, operation, storage-ring

1180

N.P. DiMonte, C. Yao
ANL, Lemont, Illinois, USA

Funding: Work supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.
With the success and reliability of the transverse feedback system installed at the Advance Photon Source (APS), an upgraded version to this system was commissioned in 2019. The previous system operated at a third of the storage-ring bunch capacity, or 432 of the available 1296 bunches. This upgrade samples all 1296 bunches which allowed corrections to be made on any selected bunch in a single storage-ring turn. To facilitate this upgrade the development of a new analog I/O board capable of 352 MHz operation was necessary. This paper discusses some of the challenges associated in processing one bunch out of 1296 bunches and how flexible the system can be in processing all 1296 bunches. We will also report on the performance of this system.

Poster WEPHA042 [10.931 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA042

About •

paper received ※ 24 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA103

Backward Compatible Update of the Timing System of WEST

network, timing, distributed, controls

1338

Y. Moudden, A. Barbuti, G. Caulier, T. Poirier, B. Santraine, B. Vincent
CEA/DRF/IRFM, St Paul Lez Durance, France

Between 2013 and 2016, the tokamak Tore Supra in operation at Cadarache (CEA-France) since 1988 underwent a major upgrade following which it was renamed WEST (Tungsten [W] Environment in Steady state Tokamak). The synchronization system however was not upgraded since 1999*. At the time, a robust design was achieved based on AMD’s TAXI chip**: clock and events are distributed from a central emitter over a star shaped network of simplex optical links to electronic crates around the tokamak. Unfortunately, spare boards were not produced in sufficient quantities and the TAXI is obsolete. In fact, multigigabit serial communication standards question the future availability of any such low rate SerDeses. Designing replacement boards provides an opportunity for a new CDR solution and extended functionalities (loss-of-lock detection, latency monitoring). Backward compatibility is a major constraint given the lack of resources for a full upgrade. We will first describe the current state of the timing network of WEST, then the implementation of a custom CDR in full firmware, using the IOSerDeses of Xilinx FPGAs and will finally provide preliminary results on development boards.
*"Upgrade of the timing system for Tore Supra long pulses", D. Moulin et al. IEEE RealTime Conference 1999
**http://hep.uchicago.edu/~thliu/projects/Pulsar/other_doc/TAXIchip.pdf

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA103

About •

paper received ※ 30 September 2019 paper accepted ※ 03 October 2020 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPHA151

A Very Lightweight Process Variable Server

controls, GUI, software, monitoring

1449

A. Sukhanov, J.P. Jamilkowski
BNL, Upton, New York, USA

Funding: Work supported by Brookhaven Science Associates, LLC under Contract No. DE-SC0012704 with the U.S. Department of Energy.
Modern instruments are often supplied with rich proprietary software tools, which makes it difficult to integrate them to an existing control systems. The liteServer is very lightweight, low latency, cross-platform network protocol for signal monitoring and control. It provides very basic functionality of popular channel access protocols like CA or pvAccess of EPICS. It supports request-reply patterns: ’info’, ’get’ and ’set’ requests and publish-subscribe pattern: ’monitor’ request. The main scope of the liteServer is: 1) provide control and monitoring for instruments supplied with proprietary software, 2) provide fastest possible Ethernet transactions, 3) make it possible to implement in FPGA without CPU core. The transport protocol is connection-less (UDP) and data serialization format is Universal Binary JSON (UBJSON). The UBJSON provides complete compatibility with the JSON specification, it is very efficient and fast. A liteServer-based system can be connected to existing control system using simple bridge program (bridges for EPICS and RHIC Ado are provided).

Poster WEPHA151 [0.383 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA151

About •

paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THCPR01

Novel FPGA-Based Instrumentation for Personnel Safety Systems in Particle Accelerator Facility

hardware, radiation, software, controls

1617

S. Pioli, M. Belli, M.M. Beretta, B. Buonomo, P. Ciambrone, D.G.C. Di Giulio, L.G. Foggetta, O. Frasciello, A. Variola
INFN/LNF, Frascati, Italy
P. Valente
INFN-Roma, Roma, Italy

Personnel safety system for particle accelerator facility involves different devices to monitor gates, shielding doors, dosimetry stations, search and emergency buttons. In order to achieve the proper reliability, these systems are developed compliant with functional safety standards involving stable technologies like relays and, recently, PLC. This work will report benchmark of a new FPGA-based system, developed at INFN-LNF, from the design to the validation phase of the prototype currently operating inside the linac bunker of Dafne. In order to achieve the compliance with functional safety standard (IEC-61508), NCRP report 88 on "Radiation Alarms and Access Control Systems" and ANSI report 43 on "Radiation Safety for the Design and Operation of Particle Accelerator", this novel instrument has been designed capable of: devices monitoring in real-time, dual modular redundancy, fail-safe, fool-proof and multi-node architecture on optical link. The aim of this project is to illustrate the feasibility of FPGA technology in the field of personnel safety and develop a standard solution for other fields like the machine protection.

Slides THCPR01 [2.928 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR01

About •

paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THCPR03

A Safety Rated FPGA Framework for Fast Safety Systems

PLC, electron, hardware, diagnostics

1626

F. Tao, B.M. Bennett, D.G. Brown, J. Jones, M.W. Stettler
SLAC, Menlo Park, California, USA

In this paper, we will introduce a generic safety-rated FPGA design template. FMEDA analysis, hardware reliability modeling, firmware development, verification and validation will be described in details to demonstrate the IEC 61508 compliant development process. In this dual redundant design, each chain consists a FPGA chip from different manufacturers to minimize the potential common cause failures. Cross checks between FPGAs and end-to-end self-checks are performed to increase the diagnostic coverage and improve the reliability. Based on this safety FPGA template, an Average Current Monitor (ACM) system is developed at SLAC with the addition of a safety PLC for diagnostics and a HMI for user interface. The overall system is deployed as part of Beam Containment System (BCS) to limit the beam current with the target Safety Integrity Level (SIL) 2.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR03

About •

paper received ※ 01 October 2019 paper accepted ※ 08 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)