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BiBTeX citation export for WEPHA035: Firmware Layer Implementation of the nBLM and icBLM Systems for ESS Project

@InProceedings{cichalewski:icalepcs2019-wepha035,
  author       = {W. Cichalewski and F.S. Alves and H. Carling and I. Dolenc Kittelmann and S. Farina and G.W. Jabłoński and W. Jałmużna and R. Kiełbik and K.E. Rosengren and T.J. Shea},
% author       = {W. Cichalewski and F.S. Alves and H. Carling and I. Dolenc Kittelmann and S. Farina and G.W. Jabłoński and others},
% author       = {W. Cichalewski and others},
  title        = {{Firmware Layer Implementation of the nBLM and icBLM Systems for ESS Project}},
  booktitle    = {Proc. ICALEPCS'19},
  pages        = {1157--1160},
  paper        = {WEPHA035},
  language     = {english},
  keywords     = {linac, neutron, FPGA, interface, simulation},
  venue        = {New York, NY, USA},
  series       = {International Conference on Accelerator and Large Experimental Physics Control Systems},
  number       = {17},
  publisher    = {JACoW Publishing, Geneva, Switzerland},
  month        = {08},
  year         = {2020},
  issn         = {2226-0358},
  isbn         = {978-3-95450-209-7},
  doi          = {10.18429/JACoW-ICALEPCS2019-WEPHA035},
  url          = {https://jacow.org/icalepcs2019/papers/wepha035.pdf},
  note         = {https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA035},
  abstract     = {Both ionization chamber Beam Loss Monitor (icBLM) and neutron Beam Loss Monitor (nBLM) systems are fundamental components of European Spallation Source (ESS) accelerator safety systems. Main responsibility of this system is instantaneous and reliable detection of accelerated proton beam loss that exceeds predefined safety threshold. Nowadays DMCS (as an in-kind partner to ESS) is responsible for beam loss detection algorithm implementation, evaluation and deployment in firmware. As a hardware platform for mentioned systems MTCA.4 based form factor electronic components have been chosen (delivered by IOXOS). This contribution focuses on both cases (nBLM and icBLM) firmware realisation presentation. Proposed and developed firmware structure and functional blocks that fulfills specified by ESS requirements are described. Additionally, some aspects of the system FPGA circuit resource usage and achieved performance is being discussed.},
}