IPAC2018 - List of Keywords (FPGA)

Paper	Title	Other Keywords	Page
TUZGBD2	Transverse and Longitudinal Bunch-by-Bunch Feedback for Storage Rings	feedback, kicker, timing, damping	1198
	T. Nakamura JASRI/SPring-8, Hyogo-ken, Japan
	Digital bunch-by-bunch feedback systems for betatron and synchrotron oscillation are powerful tools for suppression of beam instabilities and are indispensable for stable operation of storage rings. This invited talk reviews the world activities on transvers and longitudinal bunch-by-bunch feedback for storage rings.
	Slides TUZGBD2 [15.900 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-TUZGBD2
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WEPAF019	Fast Readout Algorithm for Cylindrical Beam Position Monitors Providing Good Accuracy for Particle Bunches with Large Offsets	simulation, electron, collider, pick-up	1864
	P. Thieberger, D.M. Gassner, R.L. Hulsart, R.J. Michnoff, T.A. Miller, M.G. Minty, Z. Sorrell BNL, Upton, Long Island, New York, USA A.C. Bartnik Cornell University (CLASSE), Cornell Laboratory for Accelerator-Based Sciences and Education, Ithaca, New York, USA
	Funding: This work was supported by Brookhaven Science Associates, LLC, under Contract No. DE-AC02-98CH10886 with the US Department of Energy. A simple, analytically correct algorithm is developed for calculating 'pencil' beam coordinates using the signals from an ideal cylindrical beam position monitor (BPM) with four pickup electrodes (PUEs) of infinitesimal widths. The algorithm is then applied to simulations of realistic BPMs with finite width PUEs. Surprisingly small deviations are found. Simple empirically determined correction terms reduce the deviations even further. Finally, the algorithm is used to study the impact of beam-size upon the precision of BPMs in the non-linear region. As an example of the data acquisition speed advantage, a FPGA-based BPM readout implementation of the new algorithm has been developed and characterized
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAF019
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WEPAF073	Ultra-Wideband Transverse Intra-Bunch Feedback: Beginning Development of a Next Generation 8GSa/s System	feedback, controls, interface, diagnostics	2001
	J.E. Dusatko, J.D. Fox SLAC, Menlo Park, California, USA
	Funding: US Department of Energy DE-AC02-76SF00515, US LHC Accelerator Research Program, CERN LHC Injector Upgrade Project and the US-Japan Cooperative Program in High Energy Physics. Building on the success of our 4GSa/s wideband trans-verse feedback system, we have begun development of a next generation ultra-wideband feedback processor which doubles the effective sampling rate to 8GSa/s. This higher sampling rate and proportional increase in analog band-width enable enhanced flexibility and diagnostics for accelerator transverse feedback such as control of higher-order modes, more detailed diagnostic information, im-proved SNR and two channel processing of total charge and orbit signals, with multiple pickups. Though targeted for ongoing transverse intra-bunch instability studies at the CERN SPS with a 1.7ns bunch length, the increased performance paves the way for instability control and diagnostics applications for other machines such as the HL-LHC and FCC. This paper discusses the beginning development process including an evaluation of the high-est speed AtoD and DtoA data converter devices at time of this writing and selection of the devices used in our design. It then describes the architecture of the full 8GSa/s prototype feedback processor and the design approach, which involves using both custom and commercial components enabling rapid and flexible development.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAF073
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WEPAF085	Upgrade of the CERN SPS Beam Position Measurement System	electron, electronics, pick-up, proton	2047
	M. Wendt, M. Barros Marin, A. Boccardi, T.B. Bogey, V. Kain, C. Moran Guizan, A. Topaloudis CERN, Geneva, Switzerland I. Degl'Innocenti Università di Pisa, Pisa, Italy
	The CERN Super Proton Synchrotron (SPS) is a fast cycling hadron accelerator delivering protons with momenta of up to 450 GeV/c for the Large Hadron Collider (LHC), fixed target experiments and other users such as the AWAKE plasma acceleration experiment, and also used to accelerate heavy ions. This paper presents the upgrade initiative for the SPS beam position measurement system in the frame of the CERN LHC Injector Upgrade (LIU) project. The new SPS beam position read-out electronics will be based on logarithmic amplifiers, using signals provided by the 216 existing beam position monitors, the majority of which are based on split-plane 'shoebox' technology. It will need to cover a dynamic range sufficient to manage the wide range of SPS beam intensities and bunch formatting schemes to provide turn-by-turn and averaged beam orbits along the SPS acceleration cycles. In order to avoid long coaxial cables, the front-end electronics including the digitisation, will be located inside the accelerator tunnel, with optical transmission to surface processing electronics. This represents an additional challenge in terms of radiation tolerance of electronics components and materials.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAF085
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WEPAK012	Developing Kalman Filter Based Detuning Control with a Digital SRF CW Cavity Simulator	cavity, controls, SRF, LLRF	2114
	A. Ushakov, P. Echevarria, A. Neumann HZB, Berlin, Germany
	Funding: Work supported by German Bundesministerium für Bildung und Forschung, Land Berlin, and grants of the Helmholtz Association Continuous wave operated superconducting cavities experiencing small net beam loading and thus operate potentially at narrow bandwidth require precise detuning control to reach the high stability requirements for RF fields within facilities as FEL or ERL based photon sources. Especially microphonics compensation down to sub-hertz detuning regime besides improving stability reduces the risk of rise of Lorentz force detuning driven ponderomotive instabilities. Usually the complex and second order nature of the mechanical to RF detuning transfer functions of cavity and cavity-tuner system require for more advanced control schemes. In this paper we will show the application of a Kalman filter based detuning estimator algorithm first introduced during IPAC2017 [1] to the SRF cavity simulator developed at Helmholtz Zentrum Berlin [2]. Results using the algorithm in observer mode to detuning compensation attempts in closed loop mode are presented. * A. Ushakov, P. Echevarria, A. Neumann, Proc. of IPAC 2017, Copenhagen, Denmark
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAK012
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WEPAK013	SRF Cavity Simulator for LLRF Algorithms Debugging	cavity, controls, SRF, LLRF	2118
	P. Echevarria, J. Knobloch, A. Neumann, A. Ushakov HZB, Berlin, Germany E. Aldekoa, J. Jugo University of the Basque Country, Faculty of Science and Technology, Bilbao, Spain
	Funding: Work supported by German Bundesministerium für Bildung und Forschung, Land Berlin, and grants of Helmholtz Association The availability of niobium superconducting cavities, ei-ther due to a lack of a real cavity or due to the time needed for the experiment set up (vacuum, cryogenics, cabling, etc.), is limited, and thus it can block or delay the develop-ment of new algorithms such as low level RF control. Hardware-in-the-loop simulations, where an actual cavity is replaced by an electronics system, can help to solve this issue. In this paper we present a Cavity Simulator imple-mented in a National Instruments PXI equipped with an FPGA module. This module operates with one intermedi-ate frequency input which is IQ-demodulated and fed to the electrical cavity's model, where the transmitted and re-flected voltages are calculated and IQ-modulated to gener-ate two intermediate frequency outputs. Some more ad-vanced features such as mechanical vibration modes driven by Lorentz-force detuning or external microphonics have also been implemented. This Cavity Simulator is planned to be connected to an mTCA chassis to close the loop with a LLRF control system.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAK013
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WEPAK016	RF Monitor System for SuperKEKB Injector Linac	linac, controls, data-acquisition, EPICS	2128
	H. Katagiri, M. Akemoto, D.A. Arakawa, T. Matsumoto, T. Miura, F. Qiu, Y. Yano KEK, Ibaraki, Japan
	A new radio frequency (RF) monitor system for the SuperKEKB project has been developed at the KEK in-jector linac. The RF monitor unit, which consists of an analog I/Q demodulator, ADC/DAC board, and FPGA board achieved 50-Hz data acquisition and beam mode identification. On the RF monitor, the amplitude and phase measurement precision has achieved 0.1% rms and 0.1° rms, respectively. Sixty RF monitor units have been installed in the linac. The present status of the RF monitor system will be re-ported.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAK016
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WEPAL041	FPGA Based Optical Phase Control for Coherent Laser Pulse Stacking	cavity, controls, experiment, laser	2265
	Y. Yang, L.R. Doolittle, Q. Du, G. Huang, W. Leemans, R.B. Wilcox, T. Zhou LBNL, Berkeley, California, USA A. Galvanauskas University of Michigan, Ann Arbor, Michigan, USA
	Coherent temporal pulse stacking combines the energy from a train of pulses into one pulse through a series of optical cavities. To stabilize the output energy, the cavity roundtrip phases must be precisely locked to particular values. Leveraging the LLRF expertise we have for conventional accelerators, a FPGA-based control system has been developed for optical cavity phase control. A phase measurement method, ''Modulated Impulse Response'', has been developed and implemented on FPGA. An experiment demonstrated that it can measure and lock the optical phases of four stacking cavities, leading to combination of 25 pulses into one pulse with 1.5 % RMS stability over 30 hours.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAL041
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WEPAL043	Distributed Control Architecture for an Integrated Accelerator and Experimental System	controls, hardware, software, real-time	2268
	D.J. Gibson, R.A. Marsh, B. Rusnak LLNL, Livermore, California, USA
	Funding: This work performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under Contract DE-AC52-07NA27344. A neutron imaging demonstration system is under construction at LLNL, integrating 4 MeV and 7 MeV deuteron accelerators with gas-based neutron production target the associated supply and return systems. This requires integrating a wide variety of control points from different rooms and floors of the Livermore accelerator facility at a single operator station. The control system adopted by the commercial vendor of the accelerators relies on the National Instruments cRIO platform, so that hardware system has been extended across all the beamline and experimental components. Here we present the unified, class-based framework that has been developed and implemented to connect the operator station through the deployed Real Time processors and FPGA interfaces to the hardware on the floor. Connection between the deployed processors and the operator workstations is via a standard TCP/IP network and relies on a publish/subscribe model for data distribution. This measurement and control framework has been designed to be extensible as additional control points are added, and to enable comprehensive, controllable logging of shot-correlated data at up to 300 Hz.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAL043
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WEPAL046	A New Digital Feedback and Feedforward Controller for Cavity Field Control of the LANSCE Accelerator	controls, cavity, feedback, LLRF	2277
	S. Kwon, L.J. Castellano, D.J. Knapp, J.T.M. Lyles, M.S. Prokop, A. Scheinker, P.A. Torrez LANL, Los Alamos, New Mexico, USA
	Funding: Work Supported by DOE A new digital low-level RF system was designed and has been deployed on the drift-tube-linac section of the Los Alamos Neutron Science Center(LANSCE) proton accelerator. This new system is part of a modernization of the existing analog cavity-field controls that were originally developed and put into service forty-five years ago. For stabilization of the cavity field amplitude and phase during beam loading, a proportional-integral feedback controller, a static beam feedforward controller, and an iterative learning controller working in parallel have been implemented. In this paper, the controller architecture is described, and the performances of the three controllers when beam is being actively accelerated is presented.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAL046
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WEPAL053	Dynamic Signal Analysis Based on FPGA for NSRRC DLLRF	cavity, LLRF, controls, feedback	2295
	F.Y. Chang, L.-H. Chang, M.H. Chang, S.W. Chang, L.J. Chen, F.-T. Chung, Y.T. Li, M.-C. Lin, Z.K. Liu, C.H. Lo, Ch. Wang, M.-S. Yeh, T.-C. Yu NSRRC, Hsinchu, Taiwan
	As DLLRF control system designs for SRF cavities have greatly matured and the FPGA technology has im-proved as well, it is possible now to think about incorporating dynamic signal analysis (DSA). Implementation of a DSA in the FPGA is desired to study the frequency response of the open/closed loop gain in a SRF system. Open loop gain is useful to observe the stability of a SRF system while closed loop gain can be applied to investi-gate the operational bandwidth of the system feedback and also to configure the performance of a PID controller. The DSA function was confirmed by analyzing the frequency response of a digital filter and the results of the analysis will be compared with MATLAB simulations.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAL053
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THPAK106	400 MHz Frequency/phase Detector and Counter	detector, controls, LLRF, TRIUMF	3481
	X.L. Fu, B. Ji, Z.G. Yin, T.J. Zhang CIAE, Beijing, People's Republic of China G. Dennison UBC & TRIUMF, Vancouver, British Columbia, Canada K. Fong, M.P. Laverty, Q. Zheng TRIUMF, Vancouver, Canada
	To enhance the performance and precision of TRIUMF Low Level RF system, a frequency/phase detector and counter based on FPGA is developed. The frequency/phase detector and counter is designed as a daughter board of the low level RF control system, and is connected to the mother board with mixed signal connectors. It sends the frequency error data to the PC though VXI databus, and provides two analog phase errors outputs. In current design, one single unit supports four channel discriminations of RF frequencies/phases. Preliminary tests show that the reported phase detector has a bandwidth of 400MHz. A unique implementation of frequency discrimination was carefully carried out to ensure the resolution can reach as high as 1Hz. The phase-frequency detector has been successfully applied to the Accelerator Cryo Module (ACM) system and the requirement of the low level RF control system is satisfied. After a long-term running test, the stability and reliability of the phase-frequency detector are verified.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPAK106
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THPML071	Upgrade of Digital BPM Processor at DCLS and SXFEL	FEL, cavity, software, EPICS	4807
	L.W. Lai, F.Z. Chen, Y.B. Leng, T. Wu, Y.B. Yan SSRF, Shanghai, People's Republic of China J. Chen SINAP, Shanghai, People's Republic of China
	A digital BPM processor has been developed at 2016 in SINAP for DCLS and SXFEL, which are FEL facilities built in China. The stripline BPM and cavity BPM processors share the same hardware platform and firmware, but the processing algorithms implemented in EPICS IOC on the ARM CPU are different. The capability of the ARM limits the processing speed to 10 bunches per second. Now the bunch rate of DCLS and SXFEL are going to increase from 10Hz to 50Hz. To meet the higher processing speed requirements, the processor firmware and software are upgraded in 2017. All BPM signal processing algorithms are implemented in FPGA, and EPICS IOC reads results only. After the upgrade, the processing speed reach 120 bunches per second. And this is also a good preparation for future Shanghai Hard-X ray FEL, which bunch rate is about 1MHz.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML071
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THPML099	Phase Extraction and Stabilization for Coherent Pulse Stacking	cavity, controls, laser, feedback	4895
	Y.L. Xu, W.-H. Huang, C.-X. Tang, L.X. Yan TUB, Beijing, People's Republic of China L.R. Doolittle, Q. Du, G. Huang, W. Leemans, D. Li, R.B. Wilcox, Y. Yang, T. Zhou LBNL, Berkeley, California, USA A. Galvanauskas University of Michigan, Ann Arbor, Michigan, USA
	Funding: This work was supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics, under Contract DE-AC02-05CH11231. Coherent pulse stacking (CPS) is a new time-domain coherent addition technique that stacks several optical pulses into a single output pulse, enabling high pulse energy and high average power. We model the CPS as a digital filter in the Z domain, and implement two deterministic algorithms extracting the cavity phase from limited data where only the pulse intensity is available. In a 2-stage 15-pulse CPS system, each optical cavity is stabilized at an individually-prescribed round-trip phase with 0.7 deg and 2.1 deg RMS phase errors for Stage 1 and Stage 2 respectively. Optical cavity phase control with nm accuracy ensures 1.2% intensity stability of the stacked pulse over 12 hours.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML099
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THPML101	A Novel Double Sideband-Based Phase Averaging Line for Phase Reference Distribution System	LLRF, experiment, laser, pick-up	4901
	Z.Y. Lin, Y.-C. Du, W.-H. Huang, Z. Pan, C.-X. Tang, C.-X. Tang, Y.L. Xu, J. Yang TUB, Beijing, People's Republic of China G. Huang LBNL, Berkeley, California, USA
	Coaxial cable based solution is one of the most important scheme in Phase Reference Distribution System. A novel double sideband-based phase averaging line has been developed in Tsinghua accelerator lab. The sender chassis generates the 2856 MHz signal as the forward signal and receives the 2856 MHz signal and the reflected double sideband signal from the receiver. The forward signal is phase-locked with the reference signal, and the forward signal and the sideband signal are adjusted by the FPGA virtual delay line. The preliminary experiments result shows the phase stability can achieve about 1% by signal distorted by the phase shifter.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML101
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THPML108	Distributed I/O System Based on Ethernet POWERLINK Under the EPICS Architecture	EPICS, Ethernet, distributed, network	4917
	X.K. Sun, G. Liu, Y. Song USTC/NSRL, Hefei, Anhui, People's Republic of China
	Ethernet POWERLINK (EPL) is a communication profile for Real-Time Ethernet. The communication profile meets real-time demands for the distributed system composed of multiple controllers. EPICS is a wildly used distributed control system in large scientific facilities. We design a distributed IO system based on EPL under the EPICS architecture and establish the prototype system composed of a PC and six FPGA boards. In this system, an EPICS driver based on openPOWERLINK is developed to monitor the system status. In this paper, the communication mechanism of EPL, the design of system architecture, the implementation of EPICS driver and the test results of prototype system will be described.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML108
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THPML121	Compensation of Transient Beam Loading in Ramping Synchrotrons Using a Fixed Frequency Processing Clock	cavity, feedback, LLRF, synchrotron	4957
	F.J. Galindo Guarch, J.M.M.A. Moreno Arostegui Universitat Politécnica de Catalunya, Barcelona, Spain P. Baudrenghien, F.J. Galindo Guarch CERN, Geneva, Switzerland
	Transient beam loading compensation schemes, such as One-Turn-FeedBack (OTFB), require beam synchronous processing (BSP). Swept clocks derived from the RF, and therefore harmonic to the revolution frequency, are widely used in CERN synchrotrons; this simplifies implementation with energy ramping, where the revolution frequency changes. It is however not optimal for state-of-the-art digital hardware that prefers fixed frequency clocks. An alternative to the swept clocking is the use of a deterministic protocol, for example, White Rabbit (WR): a fixed reference clock can be extracted from its data stream, while enabling digital distribution of the RF frequency among other data. New algorithms must be developed for BSP using this fixed clock and the digital data transmitted on the WR link. This is the strategy adopted for the SPS Low Level RF (LLRF) upgrade. The paper gives an overview of the technical, technological and historical motivations for such a paradigm evolution. It lists the problems of fixed clock BSP, and presents an innovative solution based on a real-time variable ratio re-sampler for implementing an OTFB with the new fixed clock scheme.
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Paper

Title

Other Keywords

Page

TUZGBD2

Transverse and Longitudinal Bunch-by-Bunch Feedback for Storage Rings

feedback, kicker, timing, damping

1198

T. Nakamura
JASRI/SPring-8, Hyogo-ken, Japan

Digital bunch-by-bunch feedback systems for betatron and synchrotron oscillation are powerful tools for suppression of beam instabilities and are indispensable for stable operation of storage rings. This invited talk reviews the world activities on transvers and longitudinal bunch-by-bunch feedback for storage rings.

Slides TUZGBD2 [15.900 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-TUZGBD2

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WEPAF019

Fast Readout Algorithm for Cylindrical Beam Position Monitors Providing Good Accuracy for Particle Bunches with Large Offsets

simulation, electron, collider, pick-up

1864

P. Thieberger, D.M. Gassner, R.L. Hulsart, R.J. Michnoff, T.A. Miller, M.G. Minty, Z. Sorrell
BNL, Upton, Long Island, New York, USA
A.C. Bartnik
Cornell University (CLASSE), Cornell Laboratory for Accelerator-Based Sciences and Education, Ithaca, New York, USA

Funding: This work was supported by Brookhaven Science Associates, LLC, under Contract No. DE-AC02-98CH10886 with the US Department of Energy.
A simple, analytically correct algorithm is developed for calculating 'pencil' beam coordinates using the signals from an ideal cylindrical beam position monitor (BPM) with four pickup electrodes (PUEs) of infinitesimal widths. The algorithm is then applied to simulations of realistic BPMs with finite width PUEs. Surprisingly small deviations are found. Simple empirically determined correction terms reduce the deviations even further. Finally, the algorithm is used to study the impact of beam-size upon the precision of BPMs in the non-linear region. As an example of the data acquisition speed advantage, a FPGA-based BPM readout implementation of the new algorithm has been developed and characterized

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAF019

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WEPAF073

Ultra-Wideband Transverse Intra-Bunch Feedback: Beginning Development of a Next Generation 8GSa/s System

feedback, controls, interface, diagnostics

2001

J.E. Dusatko, J.D. Fox
SLAC, Menlo Park, California, USA

Funding: US Department of Energy DE-AC02-76SF00515, US LHC Accelerator Research Program, CERN LHC Injector Upgrade Project and the US-Japan Cooperative Program in High Energy Physics.
Building on the success of our 4GSa/s wideband trans-verse feedback system, we have begun development of a next generation ultra-wideband feedback processor which doubles the effective sampling rate to 8GSa/s. This higher sampling rate and proportional increase in analog band-width enable enhanced flexibility and diagnostics for accelerator transverse feedback such as control of higher-order modes, more detailed diagnostic information, im-proved SNR and two channel processing of total charge and orbit signals, with multiple pickups. Though targeted for ongoing transverse intra-bunch instability studies at the CERN SPS with a 1.7ns bunch length, the increased performance paves the way for instability control and diagnostics applications for other machines such as the HL-LHC and FCC. This paper discusses the beginning development process including an evaluation of the high-est speed AtoD and DtoA data converter devices at time of this writing and selection of the devices used in our design. It then describes the architecture of the full 8GSa/s prototype feedback processor and the design approach, which involves using both custom and commercial components enabling rapid and flexible development.

DOI •

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WEPAF085

Upgrade of the CERN SPS Beam Position Measurement System

electron, electronics, pick-up, proton

2047

M. Wendt, M. Barros Marin, A. Boccardi, T.B. Bogey, V. Kain, C. Moran Guizan, A. Topaloudis
CERN, Geneva, Switzerland
I. Degl'Innocenti
Università di Pisa, Pisa, Italy

The CERN Super Proton Synchrotron (SPS) is a fast cycling hadron accelerator delivering protons with momenta of up to 450 GeV/c for the Large Hadron Collider (LHC), fixed target experiments and other users such as the AWAKE plasma acceleration experiment, and also used to accelerate heavy ions. This paper presents the upgrade initiative for the SPS beam position measurement system in the frame of the CERN LHC Injector Upgrade (LIU) project. The new SPS beam position read-out electronics will be based on logarithmic amplifiers, using signals provided by the 216 existing beam position monitors, the majority of which are based on split-plane 'shoebox' technology. It will need to cover a dynamic range sufficient to manage the wide range of SPS beam intensities and bunch formatting schemes to provide turn-by-turn and averaged beam orbits along the SPS acceleration cycles. In order to avoid long coaxial cables, the front-end electronics including the digitisation, will be located inside the accelerator tunnel, with optical transmission to surface processing electronics. This represents an additional challenge in terms of radiation tolerance of electronics components and materials.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAF085

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WEPAK012

Developing Kalman Filter Based Detuning Control with a Digital SRF CW Cavity Simulator

cavity, controls, SRF, LLRF

2114

A. Ushakov, P. Echevarria, A. Neumann
HZB, Berlin, Germany

Funding: Work supported by German Bundesministerium für Bildung und Forschung, Land Berlin, and grants of the Helmholtz Association
Continuous wave operated superconducting cavities experiencing small net beam loading and thus operate potentially at narrow bandwidth require precise detuning control to reach the high stability requirements for RF fields within facilities as FEL or ERL based photon sources. Especially microphonics compensation down to sub-hertz detuning regime besides improving stability reduces the risk of rise of Lorentz force detuning driven ponderomotive instabilities. Usually the complex and second order nature of the mechanical to RF detuning transfer functions of cavity and cavity-tuner system require for more advanced control schemes. In this paper we will show the application of a Kalman filter based detuning estimator algorithm first introduced during IPAC2017 [1] to the SRF cavity simulator developed at Helmholtz Zentrum Berlin [2]. Results using the algorithm in observer mode to detuning compensation attempts in closed loop mode are presented.
* A. Ushakov, P. Echevarria, A. Neumann, Proc. of IPAC 2017, Copenhagen, Denmark

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAK012

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WEPAK013

SRF Cavity Simulator for LLRF Algorithms Debugging

cavity, controls, SRF, LLRF

2118

P. Echevarria, J. Knobloch, A. Neumann, A. Ushakov
HZB, Berlin, Germany
E. Aldekoa, J. Jugo
University of the Basque Country, Faculty of Science and Technology, Bilbao, Spain

Funding: Work supported by German Bundesministerium für Bildung und Forschung, Land Berlin, and grants of Helmholtz Association
The availability of niobium superconducting cavities, ei-ther due to a lack of a real cavity or due to the time needed for the experiment set up (vacuum, cryogenics, cabling, etc.), is limited, and thus it can block or delay the develop-ment of new algorithms such as low level RF control. Hardware-in-the-loop simulations, where an actual cavity is replaced by an electronics system, can help to solve this issue. In this paper we present a Cavity Simulator imple-mented in a National Instruments PXI equipped with an FPGA module. This module operates with one intermedi-ate frequency input which is IQ-demodulated and fed to the electrical cavity's model, where the transmitted and re-flected voltages are calculated and IQ-modulated to gener-ate two intermediate frequency outputs. Some more ad-vanced features such as mechanical vibration modes driven by Lorentz-force detuning or external microphonics have also been implemented. This Cavity Simulator is planned to be connected to an mTCA chassis to close the loop with a LLRF control system.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAK013

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WEPAK016

RF Monitor System for SuperKEKB Injector Linac

linac, controls, data-acquisition, EPICS

2128

H. Katagiri, M. Akemoto, D.A. Arakawa, T. Matsumoto, T. Miura, F. Qiu, Y. Yano
KEK, Ibaraki, Japan

A new radio frequency (RF) monitor system for the SuperKEKB project has been developed at the KEK in-jector linac. The RF monitor unit, which consists of an analog I/Q demodulator, ADC/DAC board, and FPGA board achieved 50-Hz data acquisition and beam mode identification. On the RF monitor, the amplitude and phase measurement precision has achieved 0.1% rms and 0.1° rms, respectively. Sixty RF monitor units have been installed in the linac. The present status of the RF monitor system will be re-ported.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAK016

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WEPAL041

FPGA Based Optical Phase Control for Coherent Laser Pulse Stacking

cavity, controls, experiment, laser

2265

Y. Yang, L.R. Doolittle, Q. Du, G. Huang, W. Leemans, R.B. Wilcox, T. Zhou
LBNL, Berkeley, California, USA
A. Galvanauskas
University of Michigan, Ann Arbor, Michigan, USA

Coherent temporal pulse stacking combines the energy from a train of pulses into one pulse through a series of optical cavities. To stabilize the output energy, the cavity roundtrip phases must be precisely locked to particular values. Leveraging the LLRF expertise we have for conventional accelerators, a FPGA-based control system has been developed for optical cavity phase control. A phase measurement method, ''Modulated Impulse Response'', has been developed and implemented on FPGA. An experiment demonstrated that it can measure and lock the optical phases of four stacking cavities, leading to combination of 25 pulses into one pulse with 1.5 % RMS stability over 30 hours.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAL041

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WEPAL043

Distributed Control Architecture for an Integrated Accelerator and Experimental System

controls, hardware, software, real-time

2268

D.J. Gibson, R.A. Marsh, B. Rusnak
LLNL, Livermore, California, USA

Funding: This work performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under Contract DE-AC52-07NA27344.
A neutron imaging demonstration system is under construction at LLNL, integrating 4 MeV and 7 MeV deuteron accelerators with gas-based neutron production target the associated supply and return systems. This requires integrating a wide variety of control points from different rooms and floors of the Livermore accelerator facility at a single operator station. The control system adopted by the commercial vendor of the accelerators relies on the National Instruments cRIO platform, so that hardware system has been extended across all the beamline and experimental components. Here we present the unified, class-based framework that has been developed and implemented to connect the operator station through the deployed Real Time processors and FPGA interfaces to the hardware on the floor. Connection between the deployed processors and the operator workstations is via a standard TCP/IP network and relies on a publish/subscribe model for data distribution. This measurement and control framework has been designed to be extensible as additional control points are added, and to enable comprehensive, controllable logging of shot-correlated data at up to 300 Hz.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAL043

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WEPAL046

A New Digital Feedback and Feedforward Controller for Cavity Field Control of the LANSCE Accelerator

controls, cavity, feedback, LLRF

2277

S. Kwon, L.J. Castellano, D.J. Knapp, J.T.M. Lyles, M.S. Prokop, A. Scheinker, P.A. Torrez
LANL, Los Alamos, New Mexico, USA

Funding: Work Supported by DOE
A new digital low-level RF system was designed and has been deployed on the drift-tube-linac section of the Los Alamos Neutron Science Center(LANSCE) proton accelerator. This new system is part of a modernization of the existing analog cavity-field controls that were originally developed and put into service forty-five years ago. For stabilization of the cavity field amplitude and phase during beam loading, a proportional-integral feedback controller, a static beam feedforward controller, and an iterative learning controller working in parallel have been implemented. In this paper, the controller architecture is described, and the performances of the three controllers when beam is being actively accelerated is presented.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAL046

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WEPAL053

Dynamic Signal Analysis Based on FPGA for NSRRC DLLRF

cavity, LLRF, controls, feedback

2295

F.Y. Chang, L.-H. Chang, M.H. Chang, S.W. Chang, L.J. Chen, F.-T. Chung, Y.T. Li, M.-C. Lin, Z.K. Liu, C.H. Lo, Ch. Wang, M.-S. Yeh, T.-C. Yu
NSRRC, Hsinchu, Taiwan

As DLLRF control system designs for SRF cavities have greatly matured and the FPGA technology has im-proved as well, it is possible now to think about incorporating dynamic signal analysis (DSA). Implementation of a DSA in the FPGA is desired to study the frequency response of the open/closed loop gain in a SRF system. Open loop gain is useful to observe the stability of a SRF system while closed loop gain can be applied to investi-gate the operational bandwidth of the system feedback and also to configure the performance of a PID controller. The DSA function was confirmed by analyzing the frequency response of a digital filter and the results of the analysis will be compared with MATLAB simulations.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-WEPAL053

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THPAK106

400 MHz Frequency/phase Detector and Counter

detector, controls, LLRF, TRIUMF

3481

X.L. Fu, B. Ji, Z.G. Yin, T.J. Zhang
CIAE, Beijing, People's Republic of China
G. Dennison
UBC & TRIUMF, Vancouver, British Columbia, Canada
K. Fong, M.P. Laverty, Q. Zheng
TRIUMF, Vancouver, Canada

To enhance the performance and precision of TRIUMF Low Level RF system, a frequency/phase detector and counter based on FPGA is developed. The frequency/phase detector and counter is designed as a daughter board of the low level RF control system, and is connected to the mother board with mixed signal connectors. It sends the frequency error data to the PC though VXI databus, and provides two analog phase errors outputs. In current design, one single unit supports four channel discriminations of RF frequencies/phases. Preliminary tests show that the reported phase detector has a bandwidth of 400MHz. A unique implementation of frequency discrimination was carefully carried out to ensure the resolution can reach as high as 1Hz. The phase-frequency detector has been successfully applied to the Accelerator Cryo Module (ACM) system and the requirement of the low level RF control system is satisfied. After a long-term running test, the stability and reliability of the phase-frequency detector are verified.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPAK106

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THPML071

Upgrade of Digital BPM Processor at DCLS and SXFEL

FEL, cavity, software, EPICS

4807

L.W. Lai, F.Z. Chen, Y.B. Leng, T. Wu, Y.B. Yan
SSRF, Shanghai, People's Republic of China
J. Chen
SINAP, Shanghai, People's Republic of China

A digital BPM processor has been developed at 2016 in SINAP for DCLS and SXFEL, which are FEL facilities built in China. The stripline BPM and cavity BPM processors share the same hardware platform and firmware, but the processing algorithms implemented in EPICS IOC on the ARM CPU are different. The capability of the ARM limits the processing speed to 10 bunches per second. Now the bunch rate of DCLS and SXFEL are going to increase from 10Hz to 50Hz. To meet the higher processing speed requirements, the processor firmware and software are upgraded in 2017. All BPM signal processing algorithms are implemented in FPGA, and EPICS IOC reads results only. After the upgrade, the processing speed reach 120 bunches per second. And this is also a good preparation for future Shanghai Hard-X ray FEL, which bunch rate is about 1MHz.

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THPML099

Phase Extraction and Stabilization for Coherent Pulse Stacking

cavity, controls, laser, feedback

4895

Y.L. Xu, W.-H. Huang, C.-X. Tang, L.X. Yan
TUB, Beijing, People's Republic of China
L.R. Doolittle, Q. Du, G. Huang, W. Leemans, D. Li, R.B. Wilcox, Y. Yang, T. Zhou
LBNL, Berkeley, California, USA
A. Galvanauskas
University of Michigan, Ann Arbor, Michigan, USA

Funding: This work was supported by the U.S. Department of Energy, Office of Science, Office of High Energy Physics, under Contract DE-AC02-05CH11231.
Coherent pulse stacking (CPS) is a new time-domain coherent addition technique that stacks several optical pulses into a single output pulse, enabling high pulse energy and high average power. We model the CPS as a digital filter in the Z domain, and implement two deterministic algorithms extracting the cavity phase from limited data where only the pulse intensity is available. In a 2-stage 15-pulse CPS system, each optical cavity is stabilized at an individually-prescribed round-trip phase with 0.7 deg and 2.1 deg RMS phase errors for Stage 1 and Stage 2 respectively. Optical cavity phase control with nm accuracy ensures 1.2% intensity stability of the stacked pulse over 12 hours.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML099

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THPML101

A Novel Double Sideband-Based Phase Averaging Line for Phase Reference Distribution System

LLRF, experiment, laser, pick-up

4901

Z.Y. Lin, Y.-C. Du, W.-H. Huang, Z. Pan, C.-X. Tang, C.-X. Tang, Y.L. Xu, J. Yang
TUB, Beijing, People's Republic of China
G. Huang
LBNL, Berkeley, California, USA

Coaxial cable based solution is one of the most important scheme in Phase Reference Distribution System. A novel double sideband-based phase averaging line has been developed in Tsinghua accelerator lab. The sender chassis generates the 2856 MHz signal as the forward signal and receives the 2856 MHz signal and the reflected double sideband signal from the receiver. The forward signal is phase-locked with the reference signal, and the forward signal and the sideband signal are adjusted by the FPGA virtual delay line. The preliminary experiments result shows the phase stability can achieve about 1% by signal distorted by the phase shifter.

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THPML108

Distributed I/O System Based on Ethernet POWERLINK Under the EPICS Architecture

EPICS, Ethernet, distributed, network

4917

X.K. Sun, G. Liu, Y. Song
USTC/NSRL, Hefei, Anhui, People's Republic of China

Ethernet POWERLINK (EPL) is a communication profile for Real-Time Ethernet. The communication profile meets real-time demands for the distributed system composed of multiple controllers. EPICS is a wildly used distributed control system in large scientific facilities. We design a distributed IO system based on EPL under the EPICS architecture and establish the prototype system composed of a PC and six FPGA boards. In this system, an EPICS driver based on openPOWERLINK is developed to monitor the system status. In this paper, the communication mechanism of EPL, the design of system architecture, the implementation of EPICS driver and the test results of prototype system will be described.

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THPML121

Compensation of Transient Beam Loading in Ramping Synchrotrons Using a Fixed Frequency Processing Clock

cavity, feedback, LLRF, synchrotron

4957

F.J. Galindo Guarch, J.M.M.A. Moreno Arostegui
Universitat Politécnica de Catalunya, Barcelona, Spain
P. Baudrenghien, F.J. Galindo Guarch
CERN, Geneva, Switzerland

Transient beam loading compensation schemes, such as One-Turn-FeedBack (OTFB), require beam synchronous processing (BSP). Swept clocks derived from the RF, and therefore harmonic to the revolution frequency, are widely used in CERN synchrotrons; this simplifies implementation with energy ramping, where the revolution frequency changes. It is however not optimal for state-of-the-art digital hardware that prefers fixed frequency clocks. An alternative to the swept clocking is the use of a deterministic protocol, for example, White Rabbit (WR): a fixed reference clock can be extracted from its data stream, while enabling digital distribution of the RF frequency among other data. New algorithms must be developed for BSP using this fixed clock and the digital data transmitted on the WR link. This is the strategy adopted for the SPS Low Level RF (LLRF) upgrade. The paper gives an overview of the technical, technological and historical motivations for such a paradigm evolution. It lists the problems of fixed clock BSP, and presents an innovative solution based on a real-time variable ratio re-sampler for implementing an OTFB with the new fixed clock scheme.

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reference for this paper ※ https://doi.org/10.18429/JACoW-IPAC2018-THPML121

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