ICALEPCS2017 - List of Keywords (timing)

Paper	Title	Other Keywords	Page
MODPL01	Replacing The Engine In Your Car While You Are Still Driving It - Part II	ion, operation, controls, interface	88
	E. Björklund LANL, Los Alamos, New Mexico, USA
	Two years ago, at the 2015 ICALEPCS conference in Melbourne Australia, we presented a paper entitled 'Replacing The Engine In Your Car While You Are Still Driving It'. In that paper we described the mid-point of a very ambitious, multi-year, upgrade project involving the complete replacement of the low-level RF system, the timing system, the industrial I/O system, the beam-synchronized data acquisition system, the fast-protect reporting system, and much of the diagnostic equipment. That paper focused mostly on the timing system upgrade and presented several observations and recommendations from the perspective of the timing system and its interactions with the other systems. In this paper, now nearly three quarters of the way through our upgrade schedule, we will report on additional observations, challenges, recommendations, and lessons learned from some of the other involved systems. E.Bjorklund, 'Replacing The Engine In Your Car While You Are Still Driving It', THHC2O03, Proceedings of ICALEPCS2015, Melbourne, Australia (2015)
	Talk as video stream: https://youtu.be/_e-Wxhw-lUM
	Slides MODPL01 [4.113 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-MODPL01
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TUCPL01	Refurbishment of the ESRF Accelerator Synchronization System Using White Rabbit	ion, SRF, network, booster	224
	G. Goujon, A. Broquet, N. Janvier ESRF, Grenoble, France
	The ESRF timing system, dating from the early 90's and still in operation, is built around a centralized RF driven sequencer distributing synchronization signals along copper cables. The RF clock is broadcasted over a separate copper network. White Rabbit, offers many attractive features for the refurbishment of a synchrotron timing system, the key one being the possibility to carry RF over the White Rabbit optical fiber network. CERN having improved the feature to provide network-wide phase together with frequency control over the distributed RF, the whole technology is now mature enough to propose a White Rabbit based solution for the replacement of the ESRF system, providing flexibility and accurate time stamping of events. We describe here the main features and first performance results of the WHIST module, an ESRF development based on the White Rabbit standalone SPEC board embedding the White Rabbit protocol and a custom mezzanine (DDSIO) extending the FMC-DDS hardware to provide up to 12 programmable output signals. All WHIST modules in the network run in phase duplicates of a common RF driven sequencer. A master module broadcasts the RF and the injection trigger.
	Talk as video stream: https://youtu.be/Ege_6IGHNPU
	Slides TUCPL01 [1.595 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUCPL01
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TUCPL02	Synchronized Timing and Control System Construction of SuperKEKB Positron Damping Ring	ion, positron, linac, injection	229
	H. Sugimura, K. Furukawa, H. Kaji, F. Miyahara, T.T. Nakamura, Y. Ohnishi, S. Sasaki, M. Satoh KEK, Ibaraki, Japan
	The KEK electron/positron injector chain delivers beams for particle physics and photon science experiments. A damping ring has been constructed at the middle of the linac to generate a positron beam with sufficiently low emittance to support a 40-fold higher luminosity in the SuperKEKB asymmetric collider over the previous project of KEKB, in order to increase our understanding of flavour physics. A timing and control system for the damping ring is under construction to enable the timing synchronization and beam bucket selection between the linac, the positron damping ring and the SuperKEKB main ring. It should manage precise timing down to several picoseconds for the beam energy and bunch compression systems. Besides precise timing controls to receive and transmit positron beams, it has to meet local analysis requirements in order to measure beam properties precisely with changing the RF frequency. It is incorporating the event timing control modules from MRF and SINAP.
	Talk as video stream: https://youtu.be/BMAJimbEQB4
	Slides TUCPL02 [0.482 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUCPL02
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TUCPL04	SwissFEL Timing System: First Operational Experience	ion, FEL, controls, software	232
	B. Kalantari, R. Biffiger PSI, Villigen PSI, Switzerland
	The SwissFEL timing system builds on MRF's event system products. Performance and functional requirements have pushed MRF timing components to its newest generation (300 series) providing active delay compensation, conditional sequence events, and topology identification among others. However, employing available hardware functionalities to implement complex and varying operational demands and provide them in the control system has its own challenges. After a brief introduction to the new MRF hardware this paper describes operational aspects of the SwissFEL timing and related control system applications. We describe a new technique for beam rate control and how this scheme is used for the machine protection system (MPS). We show how a well thought modular software-side design enables us to maintain various rep rates across the facility and allows us to implement complex triggering patterns with minimum development effort. We also discuss our timestamping method and its interface to the beam synchronous data acquisition system. Further we share our experience in timing network installation, monitoring and maintenance issues during commissioning phase of the facility.
	Talk as video stream: https://youtu.be/CWx8QBpSxXc
	Slides TUCPL04 [5.381 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUCPL04
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TUCPL06	Verification of the FAIR Control System Using Deterministic Network Calculus	ion, network, controls, operation	238
	M. Schütze, S. Bondorf DISCO, Kaiserslautern, Germany M. Kreider GSI, Darmstadt, Germany M. Kreider Glyndŵr University, Wrexham, United Kingdom
	Funding: Carl Zeiss Foundation The FAIR control system (CS) is an alarm-based design and employs White Rabbit time synchronization over a GbE network to issue commands executed accurate to 1 ns. In such a network based CS, graphs of possible machine command sequences are specified in advance by physics frameworks. The actual traffic pattern, however, is determined at runtime, depending on interlocks and beam requests from experiments and accelerators. In 'unlucky' combinations, large packet bursts can delay commands beyond their deadline, potentially causing emergency shutdowns. Thus, prior verification if any possible combination of given command sequences can be delivered on time is vital to guarantee deterministic behavior of the CS. Deterministic network calculus (DNC) can derive upper bounds on message delivery latencies. This paper presents an approach for calculating worst-case descriptors of runtime traffic patterns. These so-called arrival curves are deduced from specified partial traffic sequences and are used to calculate end-to-end traffic properties. With the arrival curves and a DNC model of the FAIR CS network, a worst-case latency for specific packet flows or the whole CS can be obtained.
	Talk as video stream: https://youtu.be/t1AXzTi8kJA
	Slides TUCPL06 [0.203 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUCPL06
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TUMPL04	LCLS-II Timing Pattern Generator Configuration GUIs	ion, GUI, MMI, interface	307
	C. Bianchini, J. Browne, K.H. Kim, P. Krejcik, M. Weaver, S. Zelazny SLAC, Menlo Park, California, USA
	The LINAC Coherent Light Source II (LCLS-II) is an upgrade of the SLAC National Accelerator Laboratory LCLS facility to a superconducting LINAC with multiple destinations at different power levels. The challenge in delivering timing to a superconducting LINAC is dictated by the stability requirements for the beam power and the 1MHz rate. A timing generator will produce patterns instead of events because of the large number of event codes required. The poster explains how the stability requirements are addressed by the design of two Graphical User Interfaces (GUI). The Allow Table GUI filters the timing pattern requests respecting the Machine Protection System (MPS) defined Power Class and the electron beam dump capacities. The Timing Pattern Generator (TPG) programs Sequence Engines to deliver the beam rate configuration requested by the user. The low level program, The TPG generates the patterns, which contains the timing information propagated to the Timing Pattern Receiver (TPR). Both are implemented with an FPGA solution and configured by EPICS. The poster shows an overall design of the high-level software solutions that meet the physics requirements for LCLS-II timing.
	Slides TUMPL04 [1.030 MB]
	Poster TUMPL04 [0.883 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL04
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TUPHA064	The LIGHT Control and Interlock Systems	ion, controls, interface, proton	543
	R. Moser, H. Pavetits ADAM SA, Geneva, Switzerland
	LIGHT (Linac Image Guided Hadron Technology) is a particle therapy system* developed by Advanced Oncotherapy plc. Accelerator, control and interlock systems are developed by its subsidiary A.D.A.M. SA, a CERN spin-off. The system is being designed to accelerate protons up to 230 MeV using a modular and compact 25-meter-long linear accelerator. It is being designed to operate in pulsed mode where beam properties (energy, pulse charge and spot size) can be changed at 200 Hz. The LIGHT product will be installed in different facilities. As such, the installations will differ in accelerator and beam transfer line layouts, number of treatment rooms (with an optional gantry), facility services, equipment suppliers and equipment versions. Thus the control and interlock systems need to be extensible through configuration and modularization. To achieve this, the control system relies on a multi-tier architecture with a clear separation between front-end devices and controllers. To minimize time-to-market, the systems rely mostly on COTS hardware and software, including a timing and triggering system and a light-weight software framework to standardize front-end controllers. * The LIGHT Proton Therapy System is still subject to conformity assessment by AVO's Notified Body as well as clearance by the USA-FDA
	Poster TUPHA064 [2.678 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA064
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TUPHA079	Timing System Using FPGA for Medical Linear Accelerator Prototype at SLRI	ion, FPGA, controls, linac	589
	P. Koonpong, R. Rujanakraikarn SLRI, Nakhon Ratchasima, Thailand
	A prototype of medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI). In order to maintain the proper operation of the machine, the pulse signal is used to synchronize the various subsystems such as electron gun, RF trigger, and magnetron trigger subsystems. In this project, we design the timing system using a XilinxSpartan-3 FPGA development board with VHDL in order to achieve the desired characteristics and sequences of the timing signals for those subsystems. A LabVIEW GUI is designed to interface with the timing system in order to control the time delay and pulse width via RS-232 serial interface. The results of the system design is achieved with the pulse resolution of a 20 nsec per step for four timing channels. The time delay and pulse width for each channel can be set independently based on the SYNC reference signal.
	Poster TUPHA079 [3.417 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA079
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TUPHA082	The Timing System of HIRFL-CSR	ion, controls, operation, database	601
	W. Zhang, S. An, S.Z. Gou, K. Gu, P. Li, Y.J. Yuan, M. Yue IMP/CAS, Lanzhou, People's Republic of China
	This article gives a brief description of the timing system for Heavy Ion Research Facility in Lanzhou- Cooler Storage Ring (HIRFL-CSR). It introduces in detail mainly of the timing system architecture, hardware and software. We use standard event system architecture. The system is mainly composed of the events generator (EVG), the events receiver (EVR) and the events fan-out module. The system is the standard three-layer structure. OPI layer realizes generated and monitoring for the events. The intermediate layer is the events transmission and fan out. Device control layer performs the interpretation of the events. We adopt our R&D EVG to generate the events of virtual accelerator. At the same time, we have used our own design events fan-out module and realize distributed on the events. In equipment control layer, we use EVR design based on FPGA to interpret the events of different equipment and achieve an orderly work. The Timing System realize the ion beam injection, acceleration and extraction.
	Poster TUPHA082 [0.394 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA082
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TUPHA084	Decoupling CERN Accelerators	ion, injection, operation, linac	608
	A. Dworak, J.C. Bau CERN, Geneva, Switzerland
	The accelerator complex at CERN is a living system. Accelerators are being dismantled, upgraded or change their purpose. New accelerators are built. The changes do not happen overnight, but when they happen they may require profound changes across the handling systems. Central timings (CT), responsible for sequencing and synchronization of accelerators, are good examples of such systems. This paper shows how over the past twenty years the changes and new requirements influenced the evolution of the CTs. It describes experience gained from using the CBCM CT model, for strongly coupled accelerators, and how it led to a design of a new Dynamic Beam Negotiation (DBN) model for the AD and ELENA accelerators, which reduces the coupling, increasing accelerator independence. The paper ends with an idea how to merge strong points of both models in order to create a single generic system able to efficiently handle all involved CERN accelerators and provide more beam time to experiments and LHC.
	Poster TUPHA084 [0.477 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA084
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TUPHA086	Timing System Upgrade for Top-off Operation of HLS-II	ion, injection, storage-ring, kicker	612
	C. Li, J.L. Li, W. Li, G. Liu, J.G. Wang, L. Wang, W. Xu, K. Xuan USTC/NSRL, Hefei, Anhui, People's Republic of China
	The Hefei Light Source II (HLS-II) is a vacuum ultravi-olet (VUV) synchrotron light source. A major upgrade of the light source was finished in 2014, and the timing system was rebuilt with event-system to meet synchroni-zation requirements of the machine. The new timing system provides about 100 output signals with various interfaces. The time resolution of this system is 9.8 ns for most devices and 9 ps for the electron gun and the injec-tion kickers. The measured jitter of the output signal is less than 27 ps (RMS). In order to improve the perfor-mance of light source, the top-off operation mode has been planned. As part of this plan, both the hardware and the software of the timing system are upgraded. By ob-taining real-time data of beam measurement of storage ring, the automatic selection of the bucket is implement-ed. With any designated bunch pattern, top-off injection is achieved, and the storage ring beam can be uniform filled well.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA086
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TUPHA087	The Timing Diagram Editing and Verification Method	ion, controls, TANGO, MMI	615
	G.A. Fatkin, A.I. Senchenko BINP SB RAS, Novosibirsk, Russia G.A. Fatkin, A.I. Senchenko NSU, Novosibirsk, Russia
	Preparation and verification of the timing diagrams for the modern complex facilities with diversified timing systems is a difficult task. A mathematical method for convenient editing and verification of the timing diagrams is presented. This method is based on systems of linear equations and linear inequalities. Every timing diagram has three interconnected representations: a textual equation representation, a matrix representation and a graph (tree) representation. A prototype of software using this method was conceived in Python. This prototype allows conversion of the timing data between all three representations and its visualization.
	Poster TUPHA087 [2.162 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA087
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TUPHA088	Timing System at ESS	ion, controls, target, EPICS	618
	J. Cereijo García, T. Korhonen, J.H. Lee ESS, Lund, Sweden
	The European Spallation Source (ESS) timing system is based on the hardware developed by Micro-Research Finland (MRF). The main purposes of the timing system are: generation and distribution of synchronous clock signals and trigger events to the facility, providing a time base so that data from different systems can be time-correlated and synchronous transmission of beam-related data for for different subsystems of the facility. The timing system has a tree topology: one Event Generator (EVG) sends the events, clocks and data to an array of Event Receivers (EVRs) through an optical distribution layer (fan-out modules). The event clock frequency for ESS will be 88.0525 MHz, divided down from the bunch frequency of 352.21 MHz. An integer number of ticks of this clock will define the beam macro pulse full length, around 2.86 ms, with a repetition rate of 14 Hz. An active delay compensation mechanism will provide stability against long-term drifts. A novelty of ESS compared to other facilities is the use of the features provided by EVRs in uTCA form factor, such as trigger and clock distribution over the backplane. These EVRs are already being deployed in some systems and test stands.
	Poster TUPHA088 [3.033 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA088
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TUPHA091	A Reliable White Rabbit Network for the FAIR General Timing Machine	ion, network, Ethernet, monitoring	627
	C. Prados, J.N. Bai, A. Hahn GSI, Darmstadt, Germany A. Suresh. Suresh Hochschule Darmstadt, University of Applied Science, Darmstadt, Germany
	A new timing system based on White Rabbit (WR) is being developed for the upcoming FAIR facility at GSI in collaboration with CERN and other partners. The General Timing Machine (GTM) is responsible for the synchronization of nodes and distribution of timing events, which allows the real-time control of the accelerator equipment. WR is a time-deterministic, low latency Ethernet-based network for general data transfer and sub-ns time and frequency distribution. The FAIR WR network is considered operational only if it provides deterministic and resilient data delivery and reliable time distribution. In order to achieve this level of service, methods and techniques to increase the reliability of the GTM and WR network has been studied and evaluated. Besides, GSI has developed a network monitoring and logging system to measure the performance and detect failures of the WR network. Finally, we describe the continuous integration system at GSI and how it has improve the overall reliability of the GTM.
	Poster TUPHA091 [0.630 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA091
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TUPHA092	Two Years of FAIR General Machine Timing - Experiences and Improvements	ion, network, controls, real-time	633
	M. Kreider, R. Bär, D. Beck, A. Hahn, N. Kurz, C. Prados, S. Rauch, M. Reese, M. Zweig GSI, Darmstadt, Germany M. Kreider Glyndŵr University, Wrexham, United Kingdom
	The FAIR General Machine Timing system has been in operation at GSI since 2015 and significant progress has been made in the last two years. The CRYRING accelerator was the first machine on campus operated with the new timing system and serves as a proving ground for new control system technology to this day. A White Rabbit (WR) network was set up, connecting parts of the existing facility. The Data Master was put under control of the LSA physics core. It was enhanced with a powerful schedule language and extensive research for delay bound analysis with network calculus was undertaken. Several form factors of Timing Receivers were improved, their hard and software now being in their second release and subject to a continuous series of automated long- and short-term tests in varying network scenarios. The final goal is time-synchronization of 2000-3000 nodes using the WR Precision-Time-Protocol distribution of TAI time stamps and synchronized command and control of FAIR equipment. Promising test results for scalability and accuracy were obtained when moving from temporary small lab setups to CRYRING's control system with more than 30 nodes connected over 3 layers of WR Switches.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA092
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TUPHA161	SIP4C/C++ at CERN - Status and Lessons Learned	ion, software, operation, status	785
	S. Jensen, J.C. Bau, A. Dworak, M. Gourber-Pace, F. Hoguin, J. Lauener, F. Locci, K. Sigerud, W. Sliwinski CERN, Geneva, Switzerland
	A C/C++ software improvement process (SIP4C/C++) has been increasingly applied by the CERN accelerator Controls group since 2011, addressing technical and cultural aspects of our software development work. A first paper was presented at ICALEPCS 2013. On the technical side, a number of off-the-shelf software products have been deployed and integrated, including Atlassian Crucible (code review), Google test (unit test), Valgrind (memory profiling) and SonarQube (static code analysis). Likewise, certain in-house developments are now operational such as a Generic Makefile (compile/link/deploy), CMX (for publishing runtime process metrics) and Manifest (capturing library dependencies). SIP4C/C++ has influenced our culture by promoting integration of said products into our binaries and workflows. We describe our current status for technical solutions and how they have been integrated into our environment. Based on testimony from four project teams, we present reasons for and against adoption of individual SIP4C/C++ products and processes. Finally, we show how SIP4C/C++ has improved development and delivery processes as well as the first-line support of delivered products. http://jacow.org/ICALEPCS2013/papers/moppc087.pdf, http://jacow.org/ICALEPCS2013/posters/moppc087_poster.pdf
	Poster TUPHA161 [0.781 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA161
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TUPHA168	Improving Throughput and Latency of D-Bus to Meet the Requirements of the Fair Control System	ion, hardware, software, controls	809
	D.S. Day, A. Hahn, C. Prados, M. Reese GSI, Darmstadt, Germany
	In developing the control system for the FAIR accelerator complex we encountered strict latency and throughput contraints on the timely supply of data to devices controlling ramped magnets. In addition, the timing hardware that interfaces to the White Rabbit timing network may be shared by multiple processes on a single front-end computer. This paper describes the interprocess communication and resource-sharing system, and the consequences of using the D-Bus message bus. Then our experience of improving latency and throughput performance to meet the realtime requirements of the control system is discussed. Work is also presented on prioritisation techniques to allow time-critical services to share the bus with other components.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA168
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TUPHA205	Control in EPICS for Conditioning Test Stands for ESS	ion, EPICS, controls, cryomodule	934
	A. Gaget, A. Gomes CEA/DRF/IRFU, Gif-sur-Yvette, France Y. Lussignol CEA/DSM/IRFU, France
	CEA Irfu Saclay is involved as partner in the ESS accelerator construction through different work-packages: controls for several RF test stands, for cryomodule demonstrators, for the RFQ coupler test and for the conditioning around 120 couplers and the tests of 8 cryomodules. Due to the high number of components it is really crucial to automatize the conditioning. This paper describes how the control of these test stands was done using the ESS EPICS Environment and homemade EPICS modules. These custom modules were designed to be as generic as possible for reuse in future similar platforms and developments. They rely on the IOxOS FMC ADC3111 acquisition card, Beckhoff EtherCAT modules and the MRF timing system.
	Poster TUPHA205 [1.381 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA205
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TUSH303	Managing your Timing System as a Standard Ethernet Network	ion, network, monitoring, HOM	1007
	A. Wujek, G. Daniluk, M.M. Lipinski CERN, Geneva, Switzerland A. Rubini GNUDD, Pavia, Italy
	White Rabbit (WR) is an extension of Ethernet which allows deterministic data delivery and remote synchronization of nodes with accuracies below 1 nanosecond and jitter better than 10 ps. Because WR is Ethernet, a WR-based timing system can benefit from all standard network protocols and tools available in the Ethernet ecosystem. This paper describes the configuration, monitoring and diagnostics of a WR network using standard tools. Using the Simple Network Management Protocol (SNMP), clients can easily monitor with standard monitoring tools like Nagios, Icinga and Grafana e.g. the quality of the data link and synchronization. The former involves e.g. the number of dropped frames; The latter concerns parameters such as the latency of frame distribution and fibre delay compensation. The Link Layer Discovery Protocol (LLDP) allows discovery of the actual topology of a network. Wireshark and PTP Track Hound can intercept and help with analysis of the content of WR frames of live traffic. In order to benefit from time-proven, scalable, standard monitoring solutions, some development was needed in the WR switch and nodes.
	Poster TUSH303 [1.608 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUSH303
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THMPL09	VME Based Digitizers for Waveform Monitoring System of Linear Induction Accelerator (LIA-20)	ion, monitoring, hardware, FPGA	1291
	E.S. Kotov, A.M. Batrakov, G.A. Fatkin, A.V. Pavlenko, K.S. Shtro, M.Yu. Vasilyev BINP SB RAS, Novosibirsk, Russia G.A. Fatkin, E.S. Kotov, A.V. Pavlenko, M.Yu. Vasilyev NSU, Novosibirsk, Russia
	Waveform monitoring system plays a special role in the control system of powerful pulse installations providing the most complete information about the installation functioning and its parameters. The report describes the family of VME modules used in the waveform monitoring system of a linear induction accelerator LIA-20. In order to organize inter-module synchronization the VME-64 bus extension implemented in the VME64-BINP crates is applied in the waveform digitizers.
	Slides THMPL09 [1.653 MB]
	Poster THMPL09 [1.777 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL09
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THPHA025	LCLS-II Injector Laser System	ion, laser, controls, electron	1397
	S.C. Alverson, D.E. Anderson, S. Gilevich SLAC, Menlo Park, California, USA
	Funding: SLAC National Accelerator Lab - LCLS-II The Linac Coherent Light Source II (LCLSII) is a new Free Electron Laser (FEL) facility being built as an upgrade to the existing LCLS-I and is planned for early commissioning this year (2017) and full operation in 2020. The injector laser which hits the cathode to produce the electrons for this FEL source is conceptually similar to LCLS-I, but will utilize an upgraded controls architecture in order to be compatible with the faster repetition rate (1 MHz) of the beam. This includes moving to industrial PCs from VME and utilizing SLAC designed PCIe timing cards and camera framegrabbers. This poster discusses the overall architecture planned for this installation and discusses the reasoning behind the choices of hardware and control scheme.
	Poster THPHA025 [1.381 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA025
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THPHA062	First Production Use of the New Settings Management System for FAIR	ion, database, controls, framework	1512
	J. Fitzek, H.C. Hüther, R. Müller, A. Schaller GSI, Darmstadt, Germany
	With the successful commissioning of CRYRING, the first accelerator being operated using the new control system for FAIR (Facility for Antiproton and Ion Research), also the new settings management system is now used in a production environment for the first time. Development efforts are ongoing to realize requirements necessary to support accelerator operations at FAIR. At CRYRING, new concepts for scheduling parallel beams are being evaluated. After these successful tests and the first production use, the focus now is to include major parts of the existing facility (synchrotron SIS18, storage ring ESR and transfer lines) into the system in the context of the Controls Retrofit project. First dry runs are planned for Q4 this year. The settings management system is based on the LSA framework, that was introduced at CERN in 2001 and is being developed and enhanced together in a collaboration with GSI. Notwithstanding all successes of LSA at both institutes, a review study was set up with the goal to make the LSA framework fit for the future. Outcomes of this study and impacts on the settings management system for FAIR are being presented.
	Poster THPHA062 [4.633 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA062
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THPHA063	Status of the CLARA Control System	ion, controls, EPICS, FEL	1517
	G. Cox, R.F. Clarke, M.D. Hancock, P.W. Heath, N. Knowles, B.G. Martlew, A. Oates, P.H. Owens, W. Smith, J.T.G. Wilson STFC/DL, Daresbury, Warrington, Cheshire, United Kingdom S. Kinder DSoFt Solutions Ltd, Warrington, United Kingdom
	STFC Daresbury Laboratory has recently commissioned Phase 1 of CLARA (Compact Linear Accelerator for Research and Applications) [1], a novel FEL (Free Electron Laser) test facility focussed on the generation of ultra-short photon pulses of coherent light with high levels of stability and synchronisation. The main motivation for CLARA is to test new FEL schemes that can later be implemented on existing and future short wavelength FELs. Particular focus will be on ultra-short pulse generation, pulse stability, and synchronisation with external sources. Knowledge gained from the development and operation of CLARA will inform the aims and design of a future UK-XFEL. The control system for CLARA is a distributed control system based upon the EPICS software framework. The control system builds on experience gained from previous EPICS based facilities at Daresbury including ALICE (formerly ERLP) [2] and VELA [3]. This paper presents the current status of the CLARA control system and discusses the systems deployed for Phase 1 and future plans for later phases.
	Poster THPHA063 [2.236 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA063
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THPHA084	Synchrotron Master Frequency Reconstruction for Sub-Nanosecond Time-Resolved XMCD-PEEM Experiments	ion, experiment, fibre-optics, hardware	1577
	B. Molas, L. Aballe, M. Foerster, A. Fontsere Recuenco, O. Matilla, J. Moldes ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain
	The timing and synchronization system at the ALBA synchrotron facility is based on the well-established event-based model broadly used in the particle accelerator facilities built in the last decade. In previous systems, based on signal model architecture, the master frequency was distributed using a direct analog signal and delayed at each target where the triggers were required. However, such strategy has proven to be extremely expensive and non-scalable. In the event-based model, the data stream is generated at a continuous rate, synchronously with the master clock oscillator of the accelerator. This strategy improves the flexibility for tuning the trigger parameters remotely and reduces the costs related to maintenance tasks. On the other hand, the absence of the pure RF signal distributed in the experimental stations implies much more complexity in the performance of time-resolved experiments. Abstract here explain how these difficulties have been overcome in the ALBA timing system in order to allow the signal reconstruction of the RF master frequency at the CIRCE beamline.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA084
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THPHA088	A Time Stamping TDC for SPEC and ZEN Platforms Based on White Rabbit	ion, FPGA, monitoring, experiment	1587
	M. Brückner PSI, Villigen PSI, Switzerland R. Wischnewski DESY Zeuthen, Zeuthen, Germany
	Sub-nsec precision time synchronization is requested for data-acquisition components distributed over up to tens of km2 in modern astroparticle experiments, like upcoming Gamma-Ray and Cosmic-Ray detector arrays, to ensure optimal triggering, pattern recognition and background rejection. The White-Rabbit (WR) standard for precision time and frequency transfer is well suited for this purpose. We present two multi-channel general-purpose TDC units, which are firmware-implemented on two widely used WR-nodes: the SPEC (Spartan 6) and ZEN (Zynq) boards. Their main features: TDCs with 1 nsec resolution (default), running deadtime-free and capable of local buffering and centralized level-2 trigger architectures. The TDC stamps pulses are in absolute TAI. With off-the-shelve mezzanine boards (5ChDIO-FMC-boards), up to 5 TDC channels are available per WR-node. Higher density, customized simple I/O boards allow to turn this into 8 to 32-channel units, with an excellent price to performance ratio. The TDC units have shown excellent long-term performance in a harsh environment application at TAIGA-HiSCORE/Siberia, for the Front-End DAQ and the central GPSDO clock facility.
	Poster THPHA088 [2.880 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA088
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THPHA135	Wall Current Monitor Using PXI and LabVIEW at CERN	ion, target, LabView, controls	1699
	C. Charrondière, M. Delrieux, R. Limpens CERN, Geneva, Switzerland
	The new data acquisition system for the PS ring wall current monitors installed in the PS is able to perform higher frequency measurements of a beam bunch up to a frequency of 2.7 GHz. This is an important improvement, since the oscillating signal within the bandwidth 500-700 MHz, is related to losses of a beam bunch. The losses can be reduced by measuring the frequency and classifying the cause of the oscillations. The PXI-5661 is used to carry out spectral analysis of this signal. The acquisition is performed on a PXI running LabVIEW Real-Time and synchronized using a trigger from the accelerator timing system.
	Poster THPHA135 [2.390 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA135
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Paper

Title

Other Keywords

Page

MODPL01

Replacing The Engine In Your Car While You Are Still Driving It - Part II

ion, operation, controls, interface

88

E. Björklund
LANL, Los Alamos, New Mexico, USA

Two years ago, at the 2015 ICALEPCS conference in Melbourne Australia, we presented a paper entitled 'Replacing The Engine In Your Car While You Are Still Driving It*'. In that paper we described the mid-point of a very ambitious, multi-year, upgrade project involving the complete replacement of the low-level RF system, the timing system, the industrial I/O system, the beam-synchronized data acquisition system, the fast-protect reporting system, and much of the diagnostic equipment. That paper focused mostly on the timing system upgrade and presented several observations and recommendations from the perspective of the timing system and its interactions with the other systems. In this paper, now nearly three quarters of the way through our upgrade schedule, we will report on additional observations, challenges, recommendations, and lessons learned from some of the other involved systems.
* E.Bjorklund, 'Replacing The Engine In Your Car While You Are Still Driving It', THHC2O03, Proceedings of ICALEPCS2015, Melbourne, Australia (2015)

Talk as video stream: https://youtu.be/_e-Wxhw-lUM

Slides MODPL01 [4.113 MB]

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TUCPL01

Refurbishment of the ESRF Accelerator Synchronization System Using White Rabbit

ion, SRF, network, booster

224

G. Goujon, A. Broquet, N. Janvier
ESRF, Grenoble, France

The ESRF timing system, dating from the early 90's and still in operation, is built around a centralized RF driven sequencer distributing synchronization signals along copper cables. The RF clock is broadcasted over a separate copper network. White Rabbit, offers many attractive features for the refurbishment of a synchrotron timing system, the key one being the possibility to carry RF over the White Rabbit optical fiber network. CERN having improved the feature to provide network-wide phase together with frequency control over the distributed RF, the whole technology is now mature enough to propose a White Rabbit based solution for the replacement of the ESRF system, providing flexibility and accurate time stamping of events. We describe here the main features and first performance results of the WHIST module, an ESRF development based on the White Rabbit standalone SPEC board embedding the White Rabbit protocol and a custom mezzanine (DDSIO) extending the FMC-DDS hardware to provide up to 12 programmable output signals. All WHIST modules in the network run in phase duplicates of a common RF driven sequencer. A master module broadcasts the RF and the injection trigger.

Talk as video stream: https://youtu.be/Ege_6IGHNPU

Slides TUCPL01 [1.595 MB]

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TUCPL02

Synchronized Timing and Control System Construction of SuperKEKB Positron Damping Ring

ion, positron, linac, injection

229

H. Sugimura, K. Furukawa, H. Kaji, F. Miyahara, T.T. Nakamura, Y. Ohnishi, S. Sasaki, M. Satoh
KEK, Ibaraki, Japan

The KEK electron/positron injector chain delivers beams for particle physics and photon science experiments. A damping ring has been constructed at the middle of the linac to generate a positron beam with sufficiently low emittance to support a 40-fold higher luminosity in the SuperKEKB asymmetric collider over the previous project of KEKB, in order to increase our understanding of flavour physics. A timing and control system for the damping ring is under construction to enable the timing synchronization and beam bucket selection between the linac, the positron damping ring and the SuperKEKB main ring. It should manage precise timing down to several picoseconds for the beam energy and bunch compression systems. Besides precise timing controls to receive and transmit positron beams, it has to meet local analysis requirements in order to measure beam properties precisely with changing the RF frequency. It is incorporating the event timing control modules from MRF and SINAP.

Talk as video stream: https://youtu.be/BMAJimbEQB4

Slides TUCPL02 [0.482 MB]

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TUCPL04

SwissFEL Timing System: First Operational Experience

ion, FEL, controls, software

232

B. Kalantari, R. Biffiger
PSI, Villigen PSI, Switzerland

The SwissFEL timing system builds on MRF's event system products. Performance and functional requirements have pushed MRF timing components to its newest generation (300 series) providing active delay compensation, conditional sequence events, and topology identification among others. However, employing available hardware functionalities to implement complex and varying operational demands and provide them in the control system has its own challenges. After a brief introduction to the new MRF hardware this paper describes operational aspects of the SwissFEL timing and related control system applications. We describe a new technique for beam rate control and how this scheme is used for the machine protection system (MPS). We show how a well thought modular software-side design enables us to maintain various rep rates across the facility and allows us to implement complex triggering patterns with minimum development effort. We also discuss our timestamping method and its interface to the beam synchronous data acquisition system. Further we share our experience in timing network installation, monitoring and maintenance issues during commissioning phase of the facility.

Talk as video stream: https://youtu.be/CWx8QBpSxXc

Slides TUCPL04 [5.381 MB]

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TUCPL06

Verification of the FAIR Control System Using Deterministic Network Calculus

ion, network, controls, operation

238

M. Schütze, S. Bondorf
DISCO, Kaiserslautern, Germany
M. Kreider
GSI, Darmstadt, Germany
M. Kreider
Glyndŵr University, Wrexham, United Kingdom

Funding: Carl Zeiss Foundation
The FAIR control system (CS) is an alarm-based design and employs White Rabbit time synchronization over a GbE network to issue commands executed accurate to 1 ns. In such a network based CS, graphs of possible machine command sequences are specified in advance by physics frameworks. The actual traffic pattern, however, is determined at runtime, depending on interlocks and beam requests from experiments and accelerators. In 'unlucky' combinations, large packet bursts can delay commands beyond their deadline, potentially causing emergency shutdowns. Thus, prior verification if any possible combination of given command sequences can be delivered on time is vital to guarantee deterministic behavior of the CS. Deterministic network calculus (DNC) can derive upper bounds on message delivery latencies. This paper presents an approach for calculating worst-case descriptors of runtime traffic patterns. These so-called arrival curves are deduced from specified partial traffic sequences and are used to calculate end-to-end traffic properties. With the arrival curves and a DNC model of the FAIR CS network, a worst-case latency for specific packet flows or the whole CS can be obtained.

Talk as video stream: https://youtu.be/t1AXzTi8kJA

Slides TUCPL06 [0.203 MB]

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TUMPL04

LCLS-II Timing Pattern Generator Configuration GUIs

ion, GUI, MMI, interface

307

C. Bianchini, J. Browne, K.H. Kim, P. Krejcik, M. Weaver, S. Zelazny
SLAC, Menlo Park, California, USA

The LINAC Coherent Light Source II (LCLS-II) is an upgrade of the SLAC National Accelerator Laboratory LCLS facility to a superconducting LINAC with multiple destinations at different power levels. The challenge in delivering timing to a superconducting LINAC is dictated by the stability requirements for the beam power and the 1MHz rate. A timing generator will produce patterns instead of events because of the large number of event codes required. The poster explains how the stability requirements are addressed by the design of two Graphical User Interfaces (GUI). The Allow Table GUI filters the timing pattern requests respecting the Machine Protection System (MPS) defined Power Class and the electron beam dump capacities. The Timing Pattern Generator (TPG) programs Sequence Engines to deliver the beam rate configuration requested by the user. The low level program, The TPG generates the patterns, which contains the timing information propagated to the Timing Pattern Receiver (TPR). Both are implemented with an FPGA solution and configured by EPICS. The poster shows an overall design of the high-level software solutions that meet the physics requirements for LCLS-II timing.

Slides TUMPL04 [1.030 MB]

Poster TUMPL04 [0.883 MB]

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TUPHA064

The LIGHT Control and Interlock Systems

ion, controls, interface, proton

543

R. Moser, H. Pavetits
ADAM SA, Geneva, Switzerland

LIGHT (Linac Image Guided Hadron Technology) is a particle therapy system* developed by Advanced Oncotherapy plc. Accelerator, control and interlock systems are developed by its subsidiary A.D.A.M. SA, a CERN spin-off. The system is being designed to accelerate protons up to 230 MeV using a modular and compact 25-meter-long linear accelerator. It is being designed to operate in pulsed mode where beam properties (energy, pulse charge and spot size) can be changed at 200 Hz. The LIGHT product will be installed in different facilities. As such, the installations will differ in accelerator and beam transfer line layouts, number of treatment rooms (with an optional gantry), facility services, equipment suppliers and equipment versions. Thus the control and interlock systems need to be extensible through configuration and modularization. To achieve this, the control system relies on a multi-tier architecture with a clear separation between front-end devices and controllers. To minimize time-to-market, the systems rely mostly on COTS hardware and software, including a timing and triggering system and a light-weight software framework to standardize front-end controllers.
* The LIGHT Proton Therapy System is still subject to conformity assessment by AVO's Notified Body as well as clearance by the USA-FDA

Poster TUPHA064 [2.678 MB]

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TUPHA079

Timing System Using FPGA for Medical Linear Accelerator Prototype at SLRI

ion, FPGA, controls, linac

589

P. Koonpong, R. Rujanakraikarn
SLRI, Nakhon Ratchasima, Thailand

A prototype of medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI). In order to maintain the proper operation of the machine, the pulse signal is used to synchronize the various subsystems such as electron gun, RF trigger, and magnetron trigger subsystems. In this project, we design the timing system using a XilinxSpartan-3 FPGA development board with VHDL in order to achieve the desired characteristics and sequences of the timing signals for those subsystems. A LabVIEW GUI is designed to interface with the timing system in order to control the time delay and pulse width via RS-232 serial interface. The results of the system design is achieved with the pulse resolution of a 20 nsec per step for four timing channels. The time delay and pulse width for each channel can be set independently based on the SYNC reference signal.

Poster TUPHA079 [3.417 MB]

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TUPHA082

The Timing System of HIRFL-CSR

ion, controls, operation, database

601

W. Zhang, S. An, S.Z. Gou, K. Gu, P. Li, Y.J. Yuan, M. Yue
IMP/CAS, Lanzhou, People's Republic of China

This article gives a brief description of the timing system for Heavy Ion Research Facility in Lanzhou- Cooler Storage Ring (HIRFL-CSR). It introduces in detail mainly of the timing system architecture, hardware and software. We use standard event system architecture. The system is mainly composed of the events generator (EVG), the events receiver (EVR) and the events fan-out module. The system is the standard three-layer structure. OPI layer realizes generated and monitoring for the events. The intermediate layer is the events transmission and fan out. Device control layer performs the interpretation of the events. We adopt our R&D EVG to generate the events of virtual accelerator. At the same time, we have used our own design events fan-out module and realize distributed on the events. In equipment control layer, we use EVR design based on FPGA to interpret the events of different equipment and achieve an orderly work. The Timing System realize the ion beam injection, acceleration and extraction.

Poster TUPHA082 [0.394 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA082

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TUPHA084

Decoupling CERN Accelerators

ion, injection, operation, linac

608

A. Dworak, J.C. Bau
CERN, Geneva, Switzerland

The accelerator complex at CERN is a living system. Accelerators are being dismantled, upgraded or change their purpose. New accelerators are built. The changes do not happen overnight, but when they happen they may require profound changes across the handling systems. Central timings (CT), responsible for sequencing and synchronization of accelerators, are good examples of such systems. This paper shows how over the past twenty years the changes and new requirements influenced the evolution of the CTs. It describes experience gained from using the CBCM CT model, for strongly coupled accelerators, and how it led to a design of a new Dynamic Beam Negotiation (DBN) model for the AD and ELENA accelerators, which reduces the coupling, increasing accelerator independence. The paper ends with an idea how to merge strong points of both models in order to create a single generic system able to efficiently handle all involved CERN accelerators and provide more beam time to experiments and LHC.

Poster TUPHA084 [0.477 MB]

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TUPHA086

Timing System Upgrade for Top-off Operation of HLS-II

ion, injection, storage-ring, kicker

612

C. Li, J.L. Li, W. Li, G. Liu, J.G. Wang, L. Wang, W. Xu, K. Xuan
USTC/NSRL, Hefei, Anhui, People's Republic of China

The Hefei Light Source II (HLS-II) is a vacuum ultravi-olet (VUV) synchrotron light source. A major upgrade of the light source was finished in 2014, and the timing system was rebuilt with event-system to meet synchroni-zation requirements of the machine. The new timing system provides about 100 output signals with various interfaces. The time resolution of this system is 9.8 ns for most devices and 9 ps for the electron gun and the injec-tion kickers. The measured jitter of the output signal is less than 27 ps (RMS). In order to improve the perfor-mance of light source, the top-off operation mode has been planned. As part of this plan, both the hardware and the software of the timing system are upgraded. By ob-taining real-time data of beam measurement of storage ring, the automatic selection of the bucket is implement-ed. With any designated bunch pattern, top-off injection is achieved, and the storage ring beam can be uniform filled well.

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TUPHA087

The Timing Diagram Editing and Verification Method

ion, controls, TANGO, MMI

615

G.A. Fatkin, A.I. Senchenko
BINP SB RAS, Novosibirsk, Russia
G.A. Fatkin, A.I. Senchenko
NSU, Novosibirsk, Russia

Preparation and verification of the timing diagrams for the modern complex facilities with diversified timing systems is a difficult task. A mathematical method for convenient editing and verification of the timing diagrams is presented. This method is based on systems of linear equations and linear inequalities. Every timing diagram has three interconnected representations: a textual equation representation, a matrix representation and a graph (tree) representation. A prototype of software using this method was conceived in Python. This prototype allows conversion of the timing data between all three representations and its visualization.

Poster TUPHA087 [2.162 MB]

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TUPHA088

Timing System at ESS

ion, controls, target, EPICS

618

J. Cereijo García, T. Korhonen, J.H. Lee
ESS, Lund, Sweden

The European Spallation Source (ESS) timing system is based on the hardware developed by Micro-Research Finland (MRF). The main purposes of the timing system are: generation and distribution of synchronous clock signals and trigger events to the facility, providing a time base so that data from different systems can be time-correlated and synchronous transmission of beam-related data for for different subsystems of the facility. The timing system has a tree topology: one Event Generator (EVG) sends the events, clocks and data to an array of Event Receivers (EVRs) through an optical distribution layer (fan-out modules). The event clock frequency for ESS will be 88.0525 MHz, divided down from the bunch frequency of 352.21 MHz. An integer number of ticks of this clock will define the beam macro pulse full length, around 2.86 ms, with a repetition rate of 14 Hz. An active delay compensation mechanism will provide stability against long-term drifts. A novelty of ESS compared to other facilities is the use of the features provided by EVRs in uTCA form factor, such as trigger and clock distribution over the backplane. These EVRs are already being deployed in some systems and test stands.

Poster TUPHA088 [3.033 MB]

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TUPHA091

A Reliable White Rabbit Network for the FAIR General Timing Machine

ion, network, Ethernet, monitoring

627

C. Prados, J.N. Bai, A. Hahn
GSI, Darmstadt, Germany
A. Suresh. Suresh
Hochschule Darmstadt, University of Applied Science, Darmstadt, Germany

A new timing system based on White Rabbit (WR) is being developed for the upcoming FAIR facility at GSI in collaboration with CERN and other partners. The General Timing Machine (GTM) is responsible for the synchronization of nodes and distribution of timing events, which allows the real-time control of the accelerator equipment. WR is a time-deterministic, low latency Ethernet-based network for general data transfer and sub-ns time and frequency distribution. The FAIR WR network is considered operational only if it provides deterministic and resilient data delivery and reliable time distribution. In order to achieve this level of service, methods and techniques to increase the reliability of the GTM and WR network has been studied and evaluated. Besides, GSI has developed a network monitoring and logging system to measure the performance and detect failures of the WR network. Finally, we describe the continuous integration system at GSI and how it has improve the overall reliability of the GTM.

Poster TUPHA091 [0.630 MB]

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TUPHA092

Two Years of FAIR General Machine Timing - Experiences and Improvements

ion, network, controls, real-time

633

M. Kreider, R. Bär, D. Beck, A. Hahn, N. Kurz, C. Prados, S. Rauch, M. Reese, M. Zweig
GSI, Darmstadt, Germany
M. Kreider
Glyndŵr University, Wrexham, United Kingdom

The FAIR General Machine Timing system has been in operation at GSI since 2015 and significant progress has been made in the last two years. The CRYRING accelerator was the first machine on campus operated with the new timing system and serves as a proving ground for new control system technology to this day. A White Rabbit (WR) network was set up, connecting parts of the existing facility. The Data Master was put under control of the LSA physics core. It was enhanced with a powerful schedule language and extensive research for delay bound analysis with network calculus was undertaken. Several form factors of Timing Receivers were improved, their hard and software now being in their second release and subject to a continuous series of automated long- and short-term tests in varying network scenarios. The final goal is time-synchronization of 2000-3000 nodes using the WR Precision-Time-Protocol distribution of TAI time stamps and synchronized command and control of FAIR equipment. Promising test results for scalability and accuracy were obtained when moving from temporary small lab setups to CRYRING's control system with more than 30 nodes connected over 3 layers of WR Switches.

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TUPHA161

SIP4C/C++ at CERN - Status and Lessons Learned

ion, software, operation, status

785

S. Jensen, J.C. Bau, A. Dworak, M. Gourber-Pace, F. Hoguin, J. Lauener, F. Locci, K. Sigerud, W. Sliwinski
CERN, Geneva, Switzerland

A C/C++ software improvement process (SIP4C/C++) has been increasingly applied by the CERN accelerator Controls group since 2011, addressing technical and cultural aspects of our software development work. A first paper was presented at ICALEPCS 2013*. On the technical side, a number of off-the-shelf software products have been deployed and integrated, including Atlassian Crucible (code review), Google test (unit test), Valgrind (memory profiling) and SonarQube (static code analysis). Likewise, certain in-house developments are now operational such as a Generic Makefile (compile/link/deploy), CMX (for publishing runtime process metrics) and Manifest (capturing library dependencies). SIP4C/C++ has influenced our culture by promoting integration of said products into our binaries and workflows. We describe our current status for technical solutions and how they have been integrated into our environment. Based on testimony from four project teams, we present reasons for and against adoption of individual SIP4C/C++ products and processes. Finally, we show how SIP4C/C++ has improved development and delivery processes as well as the first-line support of delivered products.
*http://jacow.org/ICALEPCS2013/papers/moppc087.pdf, http://jacow.org/ICALEPCS2013/posters/moppc087_poster.pdf

Poster TUPHA161 [0.781 MB]

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TUPHA168

Improving Throughput and Latency of D-Bus to Meet the Requirements of the Fair Control System

ion, hardware, software, controls

809

D.S. Day, A. Hahn, C. Prados, M. Reese
GSI, Darmstadt, Germany

In developing the control system for the FAIR accelerator complex we encountered strict latency and throughput contraints on the timely supply of data to devices controlling ramped magnets. In addition, the timing hardware that interfaces to the White Rabbit timing network may be shared by multiple processes on a single front-end computer. This paper describes the interprocess communication and resource-sharing system, and the consequences of using the D-Bus message bus. Then our experience of improving latency and throughput performance to meet the realtime requirements of the control system is discussed. Work is also presented on prioritisation techniques to allow time-critical services to share the bus with other components.

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA168

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TUPHA205

Control in EPICS for Conditioning Test Stands for ESS

ion, EPICS, controls, cryomodule

934

A. Gaget, A. Gomes
CEA/DRF/IRFU, Gif-sur-Yvette, France
Y. Lussignol
CEA/DSM/IRFU, France

CEA Irfu Saclay is involved as partner in the ESS accelerator construction through different work-packages: controls for several RF test stands, for cryomodule demonstrators, for the RFQ coupler test and for the conditioning around 120 couplers and the tests of 8 cryomodules. Due to the high number of components it is really crucial to automatize the conditioning. This paper describes how the control of these test stands was done using the ESS EPICS Environment and homemade EPICS modules. These custom modules were designed to be as generic as possible for reuse in future similar platforms and developments. They rely on the IOxOS FMC ADC3111 acquisition card, Beckhoff EtherCAT modules and the MRF timing system.

Poster TUPHA205 [1.381 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA205

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TUSH303

Managing your Timing System as a Standard Ethernet Network

ion, network, monitoring, HOM

1007

A. Wujek, G. Daniluk, M.M. Lipinski
CERN, Geneva, Switzerland
A. Rubini
GNUDD, Pavia, Italy

White Rabbit (WR) is an extension of Ethernet which allows deterministic data delivery and remote synchronization of nodes with accuracies below 1 nanosecond and jitter better than 10 ps. Because WR is Ethernet, a WR-based timing system can benefit from all standard network protocols and tools available in the Ethernet ecosystem. This paper describes the configuration, monitoring and diagnostics of a WR network using standard tools. Using the Simple Network Management Protocol (SNMP), clients can easily monitor with standard monitoring tools like Nagios, Icinga and Grafana e.g. the quality of the data link and synchronization. The former involves e.g. the number of dropped frames; The latter concerns parameters such as the latency of frame distribution and fibre delay compensation. The Link Layer Discovery Protocol (LLDP) allows discovery of the actual topology of a network. Wireshark and PTP Track Hound can intercept and help with analysis of the content of WR frames of live traffic. In order to benefit from time-proven, scalable, standard monitoring solutions, some development was needed in the WR switch and nodes.

Poster TUSH303 [1.608 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUSH303

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THMPL09

VME Based Digitizers for Waveform Monitoring System of Linear Induction Accelerator (LIA-20)

ion, monitoring, hardware, FPGA

1291

E.S. Kotov, A.M. Batrakov, G.A. Fatkin, A.V. Pavlenko, K.S. Shtro, M.Yu. Vasilyev
BINP SB RAS, Novosibirsk, Russia
G.A. Fatkin, E.S. Kotov, A.V. Pavlenko, M.Yu. Vasilyev
NSU, Novosibirsk, Russia

Waveform monitoring system plays a special role in the control system of powerful pulse installations providing the most complete information about the installation functioning and its parameters. The report describes the family of VME modules used in the waveform monitoring system of a linear induction accelerator LIA-20. In order to organize inter-module synchronization the VME-64 bus extension implemented in the VME64-BINP crates is applied in the waveform digitizers.

Slides THMPL09 [1.653 MB]

Poster THMPL09 [1.777 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPL09

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THPHA025

LCLS-II Injector Laser System

ion, laser, controls, electron

1397

S.C. Alverson, D.E. Anderson, S. Gilevich
SLAC, Menlo Park, California, USA

Funding: SLAC National Accelerator Lab - LCLS-II
The Linac Coherent Light Source II (LCLSII) is a new Free Electron Laser (FEL) facility being built as an upgrade to the existing LCLS-I and is planned for early commissioning this year (2017) and full operation in 2020. The injector laser which hits the cathode to produce the electrons for this FEL source is conceptually similar to LCLS-I, but will utilize an upgraded controls architecture in order to be compatible with the faster repetition rate (1 MHz) of the beam. This includes moving to industrial PCs from VME and utilizing SLAC designed PCIe timing cards and camera framegrabbers. This poster discusses the overall architecture planned for this installation and discusses the reasoning behind the choices of hardware and control scheme.

Poster THPHA025 [1.381 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA025

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THPHA062

First Production Use of the New Settings Management System for FAIR

ion, database, controls, framework

1512

J. Fitzek, H.C. Hüther, R. Müller, A. Schaller
GSI, Darmstadt, Germany

With the successful commissioning of CRYRING, the first accelerator being operated using the new control system for FAIR (Facility for Antiproton and Ion Research), also the new settings management system is now used in a production environment for the first time. Development efforts are ongoing to realize requirements necessary to support accelerator operations at FAIR. At CRYRING, new concepts for scheduling parallel beams are being evaluated. After these successful tests and the first production use, the focus now is to include major parts of the existing facility (synchrotron SIS18, storage ring ESR and transfer lines) into the system in the context of the Controls Retrofit project. First dry runs are planned for Q4 this year. The settings management system is based on the LSA framework, that was introduced at CERN in 2001 and is being developed and enhanced together in a collaboration with GSI. Notwithstanding all successes of LSA at both institutes, a review study was set up with the goal to make the LSA framework fit for the future. Outcomes of this study and impacts on the settings management system for FAIR are being presented.

Poster THPHA062 [4.633 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA062

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THPHA063

Status of the CLARA Control System

ion, controls, EPICS, FEL

1517

G. Cox, R.F. Clarke, M.D. Hancock, P.W. Heath, N. Knowles, B.G. Martlew, A. Oates, P.H. Owens, W. Smith, J.T.G. Wilson
STFC/DL, Daresbury, Warrington, Cheshire, United Kingdom
S. Kinder
DSoFt Solutions Ltd, Warrington, United Kingdom

STFC Daresbury Laboratory has recently commissioned Phase 1 of CLARA (Compact Linear Accelerator for Research and Applications) [1], a novel FEL (Free Electron Laser) test facility focussed on the generation of ultra-short photon pulses of coherent light with high levels of stability and synchronisation. The main motivation for CLARA is to test new FEL schemes that can later be implemented on existing and future short wavelength FELs. Particular focus will be on ultra-short pulse generation, pulse stability, and synchronisation with external sources. Knowledge gained from the development and operation of CLARA will inform the aims and design of a future UK-XFEL. The control system for CLARA is a distributed control system based upon the EPICS software framework. The control system builds on experience gained from previous EPICS based facilities at Daresbury including ALICE (formerly ERLP) [2] and VELA [3]. This paper presents the current status of the CLARA control system and discusses the systems deployed for Phase 1 and future plans for later phases.

Poster THPHA063 [2.236 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA063

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THPHA084

Synchrotron Master Frequency Reconstruction for Sub-Nanosecond Time-Resolved XMCD-PEEM Experiments

ion, experiment, fibre-optics, hardware

1577

B. Molas, L. Aballe, M. Foerster, A. Fontsere Recuenco, O. Matilla, J. Moldes
ALBA-CELLS Synchrotron, Cerdanyola del Vallès, Spain

The timing and synchronization system at the ALBA synchrotron facility is based on the well-established event-based model broadly used in the particle accelerator facilities built in the last decade. In previous systems, based on signal model architecture, the master frequency was distributed using a direct analog signal and delayed at each target where the triggers were required. However, such strategy has proven to be extremely expensive and non-scalable. In the event-based model, the data stream is generated at a continuous rate, synchronously with the master clock oscillator of the accelerator. This strategy improves the flexibility for tuning the trigger parameters remotely and reduces the costs related to maintenance tasks. On the other hand, the absence of the pure RF signal distributed in the experimental stations implies much more complexity in the performance of time-resolved experiments. Abstract here explain how these difficulties have been overcome in the ALBA timing system in order to allow the signal reconstruction of the RF master frequency at the CIRCE beamline.

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA084

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THPHA088

A Time Stamping TDC for SPEC and ZEN Platforms Based on White Rabbit

ion, FPGA, monitoring, experiment

1587

M. Brückner
PSI, Villigen PSI, Switzerland
R. Wischnewski
DESY Zeuthen, Zeuthen, Germany

Sub-nsec precision time synchronization is requested for data-acquisition components distributed over up to tens of km2 in modern astroparticle experiments, like upcoming Gamma-Ray and Cosmic-Ray detector arrays, to ensure optimal triggering, pattern recognition and background rejection. The White-Rabbit (WR) standard for precision time and frequency transfer is well suited for this purpose. We present two multi-channel general-purpose TDC units, which are firmware-implemented on two widely used WR-nodes: the SPEC (Spartan 6) and ZEN (Zynq) boards. Their main features: TDCs with 1 nsec resolution (default), running deadtime-free and capable of local buffering and centralized level-2 trigger architectures. The TDC stamps pulses are in absolute TAI. With off-the-shelve mezzanine boards (5ChDIO-FMC-boards), up to 5 TDC channels are available per WR-node. Higher density, customized simple I/O boards allow to turn this into 8 to 32-channel units, with an excellent price to performance ratio. The TDC units have shown excellent long-term performance in a harsh environment application at TAIGA-HiSCORE/Siberia, for the Front-End DAQ and the central GPSDO clock facility.

Poster THPHA088 [2.880 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA088

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THPHA135

Wall Current Monitor Using PXI and LabVIEW at CERN

ion, target, LabView, controls

1699

C. Charrondière, M. Delrieux, R. Limpens
CERN, Geneva, Switzerland

The new data acquisition system for the PS ring wall current monitors installed in the PS is able to perform higher frequency measurements of a beam bunch up to a frequency of 2.7 GHz. This is an important improvement, since the oscillating signal within the bandwidth 500-700 MHz, is related to losses of a beam bunch. The losses can be reduced by measuring the frequency and classifying the cause of the oscillations. The PXI-5661 is used to carry out spectral analysis of this signal. The acquisition is performed on a PXI running LabVIEW Real-Time and synchronized using a trigger from the accelerator timing system.

Poster THPHA135 [2.390 MB]

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reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA135

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