| Paper | Title | Other Keywords | Page |
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| MOPHA100 | quasar : The Full-Stack Solution for Creation of OPC-UA Middleware | software, controls, SCADA, detector | 453 |
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| Quasar (Quick OPC-UA Server Generation Framework) enables efficient development of OPC-UA servers. The project evolved into a software ecosystem providing complete OPC-UA support for Detector Control Systems. OPC-UA servers can be modeled and generated and profit from tooling to aid development, deployment and maintenance. OPC-UA client libraries can be generated and published to users. Client-server chaining is supported. quasar was used to build OPC-UA servers for different computing platforms including server machines, credit-card computers as well as System-on-a-chip solutions. Quasar generated servers can be integrated as slave modules into other software projects written in higher-level programming languages (such as Python) to provide OPC-UA information exchange. quasar supports quick and efficient integration of OPC-UA servers into a control system based on the WinCC OA SCADA platform. The ecosystem can work with different OPC-UA stacks including 100% free and open-source ones. Thus it’s not restricted by licensing constraints. The contribution will present an overview and the evolution of the ecosystem along with example applications from ATLAS DCS and beyond. | |||
| DOI • | reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA100 | ||
| About • | paper received ※ 30 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020 | ||
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| MOPHA106 | FGC3.2: A New Generation of Embedded Controls Computer for Power Converters at CERN | controls, software, Linux, hardware | 468 |
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| Modern power converters (power supplies) at CERN are controlled by devices known as Function Generator/Controllers (FGCs), which are embedded computer systems providing function generation, current and field regulation, and state control. FGCs were originally conceived for the LHC in the early 2000s, though later generations are now increasingly being deployed in the accelerators in the LHC Injector Chain (Linac4, Booster, Proton Synchrotron and SPS) to replace obsolete equipment. A new generation of FGC known as the FGC3.2 is currently in development, which will provide for the evolving needs of the CERN accelerator complex and additionally be supplied to other HEP laboratories through CERN’s Knowledge and Technology Transfer program. This paper describes the evolution of FGCs, summarizes tests performed to evaluate candidate components for the FGC3.2 and details the final hardware and software architectures which were chosen. The new controller will make use of a multi-core ARM-based system-on-chip (SoC) running an embedded Linux operating system in contrast to earlier generations which combined a microcontroller and DSP with software running on ’bare metal’. | |||
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Poster MOPHA106 [2.986 MB] | ||
| DOI • | reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA106 | ||
| About • | paper received ※ 27 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020 | ||
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| MOPHA112 | Improving Perfomance of the MTCA System by use of PCI Express Non-Transparent Bridging and Point-To-Point PCI Express Transactions | controls, distributed, ISOL | 480 |
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| The PCI Express Standard enables one of the highest data transfer rates today. However, with a large number of modules in a MTCA system and an increasing complexity of individual MTCA components along with a growing demand for high data transfer rates to client programs performance of the overall system becomes an important key parameter. Multiprocessor systems are known to provide not only the ability for higher processing bandwidth, but also allow greater system reliability through host failover mechanisms. The use of non-transparent bridges in PCI systems supporting intelligent adapters in enterprise and multiple processors in embedded systems is a well established technology. There the non-transparent bridge acts as a gateway between the local subsystem and the system backplane. This can be ported to the PCI Express standard by replacing one of the transparent switches on the PCI Express switch with a non-transparent switch. Our experience of establishing non-transparent bridging in MTCA systems will be presented. | |||
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Poster MOPHA112 [0.452 MB] | ||
| DOI • | reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA112 | ||
| About • | paper received ※ 10 September 2019 paper accepted ※ 03 November 2019 issue date ※ 30 August 2020 | ||
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| MOPHA165 | An Embedded IOC for 100 MeV Cyclotron RF Control | EPICS, controls, cyclotron, hardware | 625 |
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| An ARM9 based embedded controller for 100 MeV cyclotron RF control has been successfully developed and tested with EPICS control software. The controller is implemented as a 3U VME long card, located in the first slot of the LLRF control crate, as a supervise module that continuously monitors the status of the RF system through a costume designed backplane and related ADCs located on other boards in the crate. For high components density and signal integrate considerations, the PCB layout adopts a 6-layer design. The Debian GNU/Linux distribution for the ARM architecture has been selected as operating system for both robustness and convenience. EPICS device support as well as Linux driver routings has been written and tested to interface database records to the on board 12 multichannel 16-bit ADCs and DACs. In the meantime, a chip selecting encoding-decoding strategy has been implemented from both software and hardware aspects to extend the SPI bus of the AT91SAM9g20 processor. The detailed software as well as hardware designed will be reported in this paper. | |||
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Poster MOPHA165 [0.344 MB] | ||
| DOI • | reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA165 | ||
| About • | paper received ※ 18 September 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020 | ||
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| WECPL05 | Migrating to Tiny Core Linux in a Control System | Linux, controls, Windows, hardware | 920 |
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| The ISIS Accelerator Controls (IAC) group currently uses a version of Microsoft Windows Embedded as its chosen Operating System (OS) for control of front-line hardware. Upgrading to the current version of the Windows Embedded OS is not possible without also upgrading hardware, or changing the way software is delivered to the hardware platform. The memory requirements are simply too large to be considered a viable option. A new alternative was sought and that process led to Tiny Core Linux being selected due to its frugal memory requirements and ability to run from a RAM-disk. This paper describes the process of migrating from Windows Embedded Standard 2009 to Tiny Core Linux as the OS platform for IAC embedded hardware. | |||
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Slides WECPL05 [1.455 MB] | ||
| DOI • | reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WECPL05 | ||
| About • | paper received ※ 27 September 2019 paper accepted ※ 09 October 2019 issue date ※ 30 August 2020 | ||
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| WEPHA040 | IRFU EPICS Environment | EPICS, hardware, software, timing | 1172 |
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The 3 years collaboration with ESS* at Lund (Sweden) has given us the opportunity to use new COTS hardware and new tools. Based on that experience, we have developed the IEE (IRFU** EPICS Environment) by retaining relevant and scalable ESS solutions. This platform centralized several functionalities, fully installed by scripting, on a server that is running on a virtual machine. The functionalities are an EPICS environment and the root file system with the kernel for each embedded systems. In order to provide homogeneous EPICS modules between all collaborators, a template was designed and used as containers for new developments. Furthermore, a development and a production workflow is also proposed and strongly recommended. Due to the current responsibility of CEA IRFU to provide an EPICS platform for SARAF** at Tel Aviv (Israel), IEE was chosen as the standard platform for the whole accelerator. This paper will present the new standard IRFU EPICS Environment based on MTCA and virtual machines.
*ESS, https://europeanspallationsource.se/ **IRFU, https://irfu.cea.fr/en/ ***SARAF, http://soreq.gov.il/mmg/eng/Pages/SARAF-Facility.aspx |
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| DOI • | reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-WEPHA040 | ||
| About • | paper received ※ 27 September 2019 paper accepted ※ 19 October 2019 issue date ※ 30 August 2020 | ||
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