PCaPAC2018 - List of Keywords (rfq)

Paper	Title	Other Keywords	Page
WEP31	Design of PLC Temperature Flow Acquisition System Based on EPICS	PLC, EPICS, interface, controls	109
	H. Zheng, H. Cao, Y.X. Chen IMP/CAS, Lanzhou, People’s Republic of China
	In the design of the ADS injector II, the RFQ cavity holds a supreme status, and the RFQ temperature and flow information are the key parameters for the cavity frequency tuning. To ensure the long-term, stable and accurate acquisition of temperature flow data is the core task of control. In this paper, the PLC temperature flow acquisition system which is based on EPICS design was described, and the EPICS driver of this PLC was developed independently. The driver uses TCP/IP connection to EPICS IOC, and the communication protocol uses the "data block overall transmission protocol", to ensure the stability of the device’s data communications. After 3 months of long-term operation inspection, this acquisition system can ensure long-term and stable acquisition of real-time temperature and flow data of the equipment, and be able to send control information to related controlled equipment. In addition, redundant PLCs and redundant IOCs were adopted in this acquisition system to make the switch to alternate channels within milliseconds once a channel fails.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-WEP31
About •	paper received ※ 09 October 2018 paper accepted ※ 15 October 2018 issue date ※ 21 January 2019
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THP15	Design and Implementation of FPGA Based Protection System for Beam Acceleration in Linear IFMIF Prototype Accelerator	controls, FPGA, EPICS, operation	195
	Y. Hirata, A. Kasugai QST, Aomori, Japan A. Jokinen, A. Marqueta Fusion for Energy, Garching, Germany H. Takahashi JAEA/J-PARC, Tokai-Mura, Naka-Gun, Ibaraki-Ken, Japan
	IFMIF (International Fusion Materials Irradiation Facility) Prototype Accelerator (LIPAc) has been developed, which is designed to produce a deuteron CW beam with a current of 125 mA at 9 MeV. After the injector commissioning, the LIPAc is entering in the second commissioning phase in which RFQ, MEBT, RF Power System and Beam Instrumentation (BI) systems have been integrated. The LCSs of LIPAc have been developed by European Home Team (EU-HT) and delivered with its subsystems; the CCS, including personnel and machine protection, timing, archiving and alarming, by Japanese Home Team (JA-HT). These have been implemented on the EPICS platform to mitigate the risk of incompatibility in the integration, which JA-HT and EU-HT are jointly carrying out to control the whole accelerator. In the CCS, some interlocks associated with measurement systems–chopper interlock, protection of BI systems, etc.–are implemented on FPGA and the condition of interlock triggering can be changed from EPICS OPIs depending on the beam conditions. The use of EPICS interface can add flexibility but still satisfy fast response and reliability requirement. The design and implementation will be presented.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-THP15
About •	paper received ※ 10 October 2018 paper accepted ※ 17 October 2018 issue date ※ 21 January 2019
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Other Keywords

Page

WEP31

Design of PLC Temperature Flow Acquisition System Based on EPICS

PLC, EPICS, interface, controls

109

H. Zheng, H. Cao, Y.X. Chen
IMP/CAS, Lanzhou, People’s Republic of China

In the design of the ADS injector II, the RFQ cavity holds a supreme status, and the RFQ temperature and flow information are the key parameters for the cavity frequency tuning. To ensure the long-term, stable and accurate acquisition of temperature flow data is the core task of control. In this paper, the PLC temperature flow acquisition system which is based on EPICS design was described, and the EPICS driver of this PLC was developed independently. The driver uses TCP/IP connection to EPICS IOC, and the communication protocol uses the "data block overall transmission protocol", to ensure the stability of the device’s data communications. After 3 months of long-term operation inspection, this acquisition system can ensure long-term and stable acquisition of real-time temperature and flow data of the equipment, and be able to send control information to related controlled equipment. In addition, redundant PLCs and redundant IOCs were adopted in this acquisition system to make the switch to alternate channels within milliseconds once a channel fails.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-WEP31

About •

paper received ※ 09 October 2018 paper accepted ※ 15 October 2018 issue date ※ 21 January 2019

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THP15

Design and Implementation of FPGA Based Protection System for Beam Acceleration in Linear IFMIF Prototype Accelerator

controls, FPGA, EPICS, operation

195

Y. Hirata, A. Kasugai
QST, Aomori, Japan
A. Jokinen, A. Marqueta
Fusion for Energy, Garching, Germany
H. Takahashi
JAEA/J-PARC, Tokai-Mura, Naka-Gun, Ibaraki-Ken, Japan

IFMIF (International Fusion Materials Irradiation Facility) Prototype Accelerator (LIPAc) has been developed, which is designed to produce a deuteron CW beam with a current of 125 mA at 9 MeV. After the injector commissioning, the LIPAc is entering in the second commissioning phase in which RFQ, MEBT, RF Power System and Beam Instrumentation (BI) systems have been integrated. The LCSs of LIPAc have been developed by European Home Team (EU-HT) and delivered with its subsystems; the CCS, including personnel and machine protection, timing, archiving and alarming, by Japanese Home Team (JA-HT). These have been implemented on the EPICS platform to mitigate the risk of incompatibility in the integration, which JA-HT and EU-HT are jointly carrying out to control the whole accelerator. In the CCS, some interlocks associated with measurement systems–chopper interlock, protection of BI systems, etc.–are implemented on FPGA and the condition of interlock triggering can be changed from EPICS OPIs depending on the beam conditions. The use of EPICS interface can add flexibility but still satisfy fast response and reliability requirement. The design and implementation will be presented.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-THP15

About •

paper received ※ 10 October 2018 paper accepted ※ 17 October 2018 issue date ※ 21 January 2019

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)