PCaPAC2018 - List of Keywords (real-time)

Paper	Title	Other Keywords	Page
WEP01	EtherCAT Driver and Tools for EPICS and Linux at PSI	EPICS, controls, Linux, PLC	22
	D. Maier-Manojlovic PSI, Villigen PSI, Switzerland
	EtherCAT bus and interface are widely used for external module and device control in accelerator environments at PSI, ranging from modulator and undulator communication and control, over motion control, basic I/O control, all the way to Machine Protection System for the new SwissFEL accelerator. A combined EPICS/Linux driver package has been developed at PSI, to allow for simple and mostly automatic setup of various EtherCAT configurations. The driver is capable of automatic scan of the existing devices and modules, followed by self-configuration and finally autonomous operation of the EtherCAT bus real-time loop. Additionally, the driver package supports the user PLC to manipulate EtherCAT data in real time, implements fast real-time (single cycle) slave-to-slave communication (skipping EPICS layer or PLC completely), features guaranteed one-shot trigger signals otherwise not supported by EPICS and much more. All the standard EtherCAT functions are supported, including the complete reprogramming of slave configurations and configuration generation for programmable slaves, such as EL6692 and EL6695 network bridges.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-WEP01
About •	paper received ※ 08 October 2018 paper accepted ※ 16 October 2018 issue date ※ 21 January 2019
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEP06	Data Archiving and Visualization of IRFEL	FEL, EPICS, interface, status	41
	Y. Song, X. Chen, C. Li, G. Liu, J.G. Wang, K. Xuan USTC/NSRL, Hefei, Anhui, People’s Republic of China
	Funding: Work supported by National Natural Science Foundation of China (No.11375186) An Infrared Free Electron Laser Light (IRFEL) is being constructed at National Synchrotron Radiation Laboratory. The EPICS Archiver Appliance provides the functions of historical data acquisition, archiving, migration, retrieval and management in the IRFEL facility. A Single-Page Web Application is developed for the data visualization based on Vue.js framework and Highcharts JavaScirpt library. A unified interface is developed for the visualization to integrate multiple data sources and provide the same retrieval entry of the historical data from EPICS Archiver Appliance, the real-time data from EPICS IOC, the statistical data from database and the alarm information from the Phoebus. This paper will describe the implementation details of data archiving and visualization of IRFEL.
	Poster WEP06 [0.841 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-WEP06
About •	paper received ※ 09 October 2018 paper accepted ※ 16 October 2018 issue date ※ 21 January 2019
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THP04	Real-time and Detailed Provision of J-PARC Accelerator Operation Information from the Accelerator Control LAN to the Office LAN	controls, operation, status, EPICS	167
	S. Yamada J-PARC, KEK & JAEA, Ibaraki-ken, Japan
	J-PARC Main Ring (MR) is a high-intensity proton synchrotron whose control system is developed based on EPICS.　It started its beam operation in 2008, and since 2009 has been delivering beam to the T2K neutrino experiment and hadron experiments.　Over the past decade, MR have become more sophisticated and more stable driving is required.　Along with this, demands arose from users and experts of equipment such that acquiring detailed and real-time information on the apparatus from the office LAN.　On the other hand, the accelerator control system is quarantined from the office LAN with firewall for security reasons.　Therefore, despite being intentional or not, manipulating any equipment in the accelerator control LAN shall be prohibited from the office LAN.　This article describes construction and prospects of such an one-way gateway system such that information is relayed via EPICS from accelerator control LAN to the office LAN while minimizing influence in the opposite direction.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-THP04
About •	paper received ※ 14 October 2018 paper accepted ※ 25 April 2019 issue date ※ 21 January 2019
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THP13	The Development of a FPGA Based Front End Safety Interlock System	controls, FPGA, EPICS, status	189
	J.-Y. Chuang, C.-C. Chang, C.M. Cheng, Y.Z. Lin, I.C. Sheng, Y.C. Yang NSRRC, Hsinchu, Taiwan
	A front end (FE) safety interlock control system was designed to protect humans and the machine integrity during operation. Since stability and reliability are an important requirement in this system, we developed a FPGA based system to control a safety logic for interlock protection. The integration of the FPGA, Real-time and redundant fail-safe system in the FE interlock system enables us to provide a safe protection with EPICS com-munication and hardware protection functions.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-THP13
About •	paper received ※ 10 October 2018 paper accepted ※ 15 October 2018 issue date ※ 21 January 2019
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Other Keywords

Page

WEP01

EtherCAT Driver and Tools for EPICS and Linux at PSI

EPICS, controls, Linux, PLC

22

D. Maier-Manojlovic
PSI, Villigen PSI, Switzerland

EtherCAT bus and interface are widely used for external module and device control in accelerator environments at PSI, ranging from modulator and undulator communication and control, over motion control, basic I/O control, all the way to Machine Protection System for the new SwissFEL accelerator. A combined EPICS/Linux driver package has been developed at PSI, to allow for simple and mostly automatic setup of various EtherCAT configurations. The driver is capable of automatic scan of the existing devices and modules, followed by self-configuration and finally autonomous operation of the EtherCAT bus real-time loop. Additionally, the driver package supports the user PLC to manipulate EtherCAT data in real time, implements fast real-time (single cycle) slave-to-slave communication (skipping EPICS layer or PLC completely), features guaranteed one-shot trigger signals otherwise not supported by EPICS and much more. All the standard EtherCAT functions are supported, including the complete reprogramming of slave configurations and configuration generation for programmable slaves, such as EL6692 and EL6695 network bridges.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-WEP01

About •

paper received ※ 08 October 2018 paper accepted ※ 16 October 2018 issue date ※ 21 January 2019

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEP06

Data Archiving and Visualization of IRFEL

FEL, EPICS, interface, status

41

Y. Song, X. Chen, C. Li, G. Liu, J.G. Wang, K. Xuan
USTC/NSRL, Hefei, Anhui, People’s Republic of China

Funding: Work supported by National Natural Science Foundation of China (No.11375186)
An Infrared Free Electron Laser Light (IRFEL) is being constructed at National Synchrotron Radiation Laboratory. The EPICS Archiver Appliance provides the functions of historical data acquisition, archiving, migration, retrieval and management in the IRFEL facility. A Single-Page Web Application is developed for the data visualization based on Vue.js framework and Highcharts JavaScirpt library. A unified interface is developed for the visualization to integrate multiple data sources and provide the same retrieval entry of the historical data from EPICS Archiver Appliance, the real-time data from EPICS IOC, the statistical data from database and the alarm information from the Phoebus. This paper will describe the implementation details of data archiving and visualization of IRFEL.

Poster WEP06 [0.841 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-WEP06

About •

paper received ※ 09 October 2018 paper accepted ※ 16 October 2018 issue date ※ 21 January 2019

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THP04

Real-time and Detailed Provision of J-PARC Accelerator Operation Information from the Accelerator Control LAN to the Office LAN

controls, operation, status, EPICS

167

S. Yamada
J-PARC, KEK & JAEA, Ibaraki-ken, Japan

J-PARC Main Ring (MR) is a high-intensity proton synchrotron whose control system is developed based on EPICS.　It started its beam operation in 2008, and since 2009 has been delivering beam to the T2K neutrino experiment and hadron experiments.　Over the past decade, MR have become more sophisticated and more stable driving is required.　Along with this, demands arose from users and experts of equipment such that acquiring detailed and real-time information on the apparatus from the office LAN.　On the other hand, the accelerator control system is quarantined from the office LAN with firewall for security reasons.　Therefore, despite being intentional or not, manipulating any equipment in the accelerator control LAN shall be prohibited from the office LAN.　This article describes construction and prospects of such an one-way gateway system such that information is relayed via EPICS from accelerator control LAN to the office LAN while minimizing influence in the opposite direction.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-THP04

About •

paper received ※ 14 October 2018 paper accepted ※ 25 April 2019 issue date ※ 21 January 2019

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THP13

The Development of a FPGA Based Front End Safety Interlock System

controls, FPGA, EPICS, status

189

J.-Y. Chuang, C.-C. Chang, C.M. Cheng, Y.Z. Lin, I.C. Sheng, Y.C. Yang
NSRRC, Hsinchu, Taiwan

A front end (FE) safety interlock control system was designed to protect humans and the machine integrity during operation. Since stability and reliability are an important requirement in this system, we developed a FPGA based system to control a safety logic for interlock protection. The integration of the FPGA, Real-time and redundant fail-safe system in the FE interlock system enables us to provide a safe protection with EPICS com-munication and hardware protection functions.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2018-THP13

About •

paper received ※ 10 October 2018 paper accepted ※ 15 October 2018 issue date ※ 21 January 2019

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)