PCaPAC2016 - List of Keywords (framework)

Paper	Title	Other Keywords	Page
THDAPLCO03	Gateware and Software Frameworks for Sirius BPM Electronics	ion, interface, hardware, controls	84
	L.M. Russo, J.V. Ferreira Filho LNLS, Campinas, Brazil
	The Brazilian Synchrotron Light Laboratory (LNLS) is developing a BPM system based on the MicroTCA.4 standard comprised of AMC FPGA boards carrying FMC digitizers and an AMC CPU module. In order to integrate all of the boards into a solution and to support future applications, two frameworks were developed. The first one, gateware framework, is composed of a set of Wishbone B4 compatible modules and tools that build up the system foundation, including: PCIe Wishbone master; FMC digitizer interfaces; data acquisition engines and trigger modules. The gateware also supports the Self-Describing Bus (SDB), developed by CERN/GSI. The second one, software framework, is based on the ZeroMQ messaging library and aims to provide an extensible way of supporting new functionalities to different boards. To achieve this, this framework has a multilayered architecture, decoupling its four main components: (i) hardware communication protocol; (ii) reactor-based dispatch engine; (iii) business logic, comprising of the specific board functionalities; (iv) standard RPC-like interface to clients. In this paper, motivations, challenges and limitations of both frameworks will be discussed.
	Slides THDAPLCO03 [6.356 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2016-THDAPLCO03
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THDAPLCO06	A Framework for Development and Test of xTCA Modules With FPGA Based Systems for Particle Detectors	ion, controls, FPGA, interface	88
	M. Vaz, A.M. Cascadan, V.F. Ferreira, T. Paiva, L.A. Ramalho, A.A. Shinoda NCC UNESP, São Paulo, Brazil
	This work describes a framework to develop firmware for ATCA carrier boards with FPGA. It is composed of an ATCA IPMI protocol implementation for environmental monitoring and control, and a companion XVC protocol implementation for remote FPGA configuration and system debugging. A study case is also presented of the development of a setup to validate a Level 1 Tracker Trigger System proposed for CMS at HL-LHC.
	Slides THDAPLCO06 [4.734 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2016-THDAPLCO06
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Other Keywords

Page

THDAPLCO03

Gateware and Software Frameworks for Sirius BPM Electronics

ion, interface, hardware, controls

84

L.M. Russo, J.V. Ferreira Filho
LNLS, Campinas, Brazil

The Brazilian Synchrotron Light Laboratory (LNLS) is developing a BPM system based on the MicroTCA.4 standard comprised of AMC FPGA boards carrying FMC digitizers and an AMC CPU module. In order to integrate all of the boards into a solution and to support future applications, two frameworks were developed. The first one, gateware framework, is composed of a set of Wishbone B4 compatible modules and tools that build up the system foundation, including: PCIe Wishbone master; FMC digitizer interfaces; data acquisition engines and trigger modules. The gateware also supports the Self-Describing Bus (SDB), developed by CERN/GSI. The second one, software framework, is based on the ZeroMQ messaging library and aims to provide an extensible way of supporting new functionalities to different boards. To achieve this, this framework has a multilayered architecture, decoupling its four main components: (i) hardware communication protocol; (ii) reactor-based dispatch engine; (iii) business logic, comprising of the specific board functionalities; (iv) standard RPC-like interface to clients. In this paper, motivations, challenges and limitations of both frameworks will be discussed.

Slides THDAPLCO03 [6.356 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2016-THDAPLCO03

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THDAPLCO06

A Framework for Development and Test of xTCA Modules With FPGA Based Systems for Particle Detectors

ion, controls, FPGA, interface

88

M. Vaz, A.M. Cascadan, V.F. Ferreira, T. Paiva, L.A. Ramalho, A.A. Shinoda
NCC UNESP, São Paulo, Brazil

This work describes a framework to develop firmware for ATCA carrier boards with FPGA. It is composed of an ATCA IPMI protocol implementation for environmental monitoring and control, and a companion XVC protocol implementation for remote FPGA configuration and system debugging. A study case is also presented of the development of a setup to validate a Level 1 Tracker Trigger System proposed for CMS at HL-LHC.

Slides THDAPLCO06 [4.734 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-PCaPAC2016-THDAPLCO06

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)