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TY - CONF AU - Russo, L.M. AU - Ferreira Filho, J.V. ED - Schaa, Volker RW TI - Gateware and Software Frameworks for Sirius BPM Electronics J2 - Proc. of PCaPAC2016, Campinas, Brazil, October 2528, 2016 C1 - Campinas, Brazil T2 - International Workshop on Personal Computers and Particle Accelerator Controls T3 - 11 LA - english AB - The Brazilian Synchrotron Light Laboratory (LNLS) is developing a BPM system based on the MicroTCA.4 standard comprised of AMC FPGA boards carrying FMC digitizers and an AMC CPU module. In order to integrate all of the boards into a solution and to support future applications, two frameworks were developed. The first one, gateware framework, is composed of a set of Wishbone B4 compatible modules and tools that build up the system foundation, including: PCIe Wishbone master; FMC digitizer interfaces; data acquisition engines and trigger modules. The gateware also supports the Self-Describing Bus (SDB), developed by CERN/GSI. The second one, software framework, is based on the ZeroMQ messaging library and aims to provide an extensible way of supporting new functionalities to different boards. To achieve this, this framework has a multilayered architecture, decoupling its four main components: (i) hardware communication protocol; (ii) reactor-based dispatch engine; (iii) business logic, comprising of the specific board functionalities; (iv) standard RPC-like interface to clients. In this paper, motivations, challenges and limitations of both frameworks will be discussed. PB - JACoW CP - Geneva, Switzerland SP - 84 EP - 87 KW - ion KW - framework KW - interface KW - hardware KW - controls DA - 2017/09 PY - 2017 SN - 978-3-95450-189-2 DO - 10.18429/JACoW-PCaPAC2016-THDAPLCO03 UR - http://jacow.org/pcapac2016/papers/thdaplco03.pdf ER -