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Norum, W. E.

Paper Title Page
TUP036 Application Software for the BSP-100 Beam Position Monitor at the APS 167
 
  • H. Shang, G. Decker, L. Emery, W. E. Norum, R. Soliday
    ANL, Argonne
 
  Funding: Work supported by U. S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.

The BSP-100 beam position monitor (BPM) was commissioned and installed at the Advanced Photon Source (APS) in a fraction of the ring as an upgrade to the present turn-by-turn BPMs. Keeping the same rf front end of the present BPMs, the BSP-100 BPM adds a high-speed analog-to-digital converter and uses a field-programmable gate array (FPGA) to perform the signal processing. The main advantage of the new system is a much better signal-to-noise ratio as all the bunches in the stored beam can now be (selectively) sampled each turn. The implementation requires a much more complex timing control. We report on the high-level software that controls, saves, restores, and compares the timing of the BSP-100 BPM. This software uses Tcl/Tk for the graphical user interface, the SDDS toolkit for data processing, and SDDS-EPICS compliant tools for saving and restoring.

 
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TUP059 Commissioning of the FPGA-Based Transverse Feedback System at the Advanced Photon Source 218
 
  • N. P. Di Monte, W. E. Norum, C. Yao
    ANL, Argonne
 
  Funding: Work supported by U. S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.

The Advanced Photon Source installed a Transverse Feedback System to correct the instability in the electron beam during single bunch mode. This instability manifests itself when a large amount of current is present in the beam. The only method currently formerly available to correct the instability was through chromaticity correction. The Transverse Feedback System deals with the instability without requiring changes to the ring chromaticity. Initial testing revealed issues with the input and output electronics. This paper will discuss these issues, their resolution and many other enhancements to the FPGA-based system.

 
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TUP091 Linac Coherent Light Source (LCLS) Undulator Line Control System* 290
 
  • J. Z. Xu, N. D. Arnold, R. Laird, W. E. Norum, S. E. Shoaf, S. J. Stein, S. Xu
    ANL, Argonne
 
  The 132-meter-long Linac Coherent Light Source (LCLS) undulator line consists of 33 identical undulator segments situated in a co-linear fashion. An EPICS-based turn-key control system has been designed and delivered to the LCLS project by the Advanced Photon Source (APS). The control system is responsible for a myriad of motion and feedback channels for each segment including two linear and five nonlinear motions with micron-level accuracy, numerous absolute position readbacks, and multiple temperature sensors. With the large distance covered in the undulator line tunnel, it was decided to distribute the controls duty to multiple instances of control hardware located at each segment within the tunnel itself. A detailed description of the control system and performance results is reported.

*Work at Argonne was supported by the U. S. Department of Energy, Office of Science, Office of Basic Energy Sciences under Contract No DE-AC02-06CH11357.

 
WEP031 Development of a New Phase Detector for the APS Linac 468
 
  • A. F. Pietryla, A. E. Grelick, W. E. Norum
    ANL, Argonne
 
  Funding: Work supported by U. S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under contract No. DE-AC02-06CH11357

An effort is being made to upgrade the Advanced Photon Source Linac rf phase detector system. The decision was made to replace the current phase measurement system, which is based on a Los Alamos designed analog vector detector module, with a digital I/Q method. As an initial step we reconfigured one of our current 8-channel, 14-bit ADC designs, originally developed for the storage ring beam position monitor system, to perform the I/Q sampling and the phase and magnitude computations. This paper discusses the current board design, proposed modifications to optimize the board for this application, and field programmable gate array design.

 
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