Cattin, M.

Paper	Title	Page
TUC004	The White Rabbit Project	93
	J. Serrano, P. Alvarez, M. Cattin, E. G. Cota, J. H. Lewis, P. M. Oliveira Fernandes Moreira, T. Wlostowski CERN, Geneva R. Baer, T. Fleck, M. Kreider, C. Prados, S. Rauch GSI, Darmstadt J. Dedic Cosylab, Ljubljana G. Gaderer, P. Loschmidt Austrian Academy of Sciences, Wien
	Reliable, fast and deterministic transmission of control information in a network is a need for many distributed systems. One example is timing systems, where a reference frequency is used to accurately schedule time-critical messages. The White Rabbit (WR) project is a multi-laboratory and multi-company effort to bring together the best of the data transfer and timing worlds in a completely open design. It takes advantage of the latest developments for improving timing over Ethernet, such as IEEE 1588 (Precision Time Protocol) and Synchronous Ethernet. The presented approach aims for a general purpose, fieldbus-like transmission system, which provides deterministic data and timing (sub-ns accuracy and ps jitter) to around 1000 stations. It automatically compensates for fiber lengths in the order of 10 km. This paper describes the WR design goals and the specification used for the project. It goes on to describe the central component of the WR system structure - the WR switch - with theoretical considerations about the requirements. Finally, it presents real timing measurements for the first prototypes of WR hardware.
WEB002	FPGA Mezzanine Cards for CERN's Accelerator Control System	376
	P. Alvarez, M. Cattin, J. H. Lewis, J. Serrano, T. Wlostowski CERN, Geneva
	Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, uTCA and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed systems. Initial plans include IO mezzanines for 100MS/s ADCs and DACs, digital drivers and inputs, high accuracy time tag units and fine delay generators.
	Slides