Keyword: timing
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THPSC076 Host-Based System to Control the Accelerator controls, operation, data-acquisition, feedback 709
 
  • V.N. Zamriy
    JINR, Dubna, Moscow Region, Russia
 
  The report discusses development of the host-based data acquisition system to control the accelerator. We consider modes of timing and allocation of operations of the system node. The time of any working cycle, rate of a data flow and an amount of serviced tasks are coordinated with characteristics of the node. Estimations of the readout rate of the data and the waiting time demonstrate the system efficiency. The data acquisition technique has been developed to provide checking of pulse parameters and control the linac LUE-200 of the neutron source IREN*.
* Ju. Becher et al. "The LUE-200 accelerator at the IREN facility: current status and development", Physics of Elementary Particles and Nuclei: Letters, 11, 1029-1039 (2014).
 
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THPSC081 VME Based Digitizers for Waveform Monitoring System of Linear Induction Accelerator LIA-20 monitoring, controls, hardware, induction 721
 
  • E.S. Kotov, A.M. Batrakov, G.A. Fatkin, A.V. Pavlenko, K.S. Shtro, M.Yu. Vasilyev
    BINP SB RAS, Novosibirsk, Russia
  • G.A. Fatkin, E.S. Kotov, A.V. Pavlenko, M.Yu. Vasilyev
    NSU, Novosibirsk, Russia
 
  The Linear Induction Accelerator LIA-20 is being created at the Budker Institute of Nuclear Physics. Waveform monitoring system (WMS) is an important part of LIA-20 control system. WMS includes "slow" and "fast" monitoring subsystems. Three kinds of digitizers have been developed for WMS. "Slow" subsystem is based on ADCx32. This digitizer uses four 8 channel multiplexed SAR ADCs (8 us conversion cycle) with 12-bit resolution. Main feature of this module is program configurable channel sequencing, which allows to measure signals with different timing characteristics. Two types of digitizers are involved in "fast" subsystem. The first one, ADC4x250-4CH, is 4-channel 250 MSPS digitizer. The second one, ADC4x250-1CH, is single channel digitizer with sample rate of 1 GSPS. Resolution of both devices is 12 bit. "Fast" modules are based on the common hardware. This paper describes hardware and software architecture of these modules.  
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