Keyword: embedded
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TUMPL03 New EPICS/RTEMS IOC Based on Altera SOC at Jefferson Lab ion, EPICS, FPGA, controls 304
 
  • J. Yan, T.L. Allison, B. Bevins, A. Cuffe, C. Seaton
    JLab, Newport News, Virginia, USA
  
  A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA was designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via u-boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDRs SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications at runtime. U-boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run the RTEMS and EPICS. The standard SoC IOC board would be mounted in a chassis and connected to a daughter card via a standard HSMC connector. The first design of the SoC IOC will be compatible with our current PC104 IOCs, which have been running on our accelerator control system for 10 years. Eventually, the standard SOC IOCS would be the next generation of low-level IOC for the Accelerator control at Jefferson Lab.
Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177. 		 
slides icon Slides TUMPL03 [1.094 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUMPL03  
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TUPHA020 MATLAB Control Applications Embedded Into Epics Process Controllers (IOC) and their Impact on Facility Operations at Paul Scherrer Institute ion, controls, EPICS, network 416
 
  • P. Chevtsov, T. Pal
    PSI, Villigen PSI, Switzerland
  • M. Dach
    Dach Consulting GmbH, Brugg, Switzerland
  
  An automated tool for converting MATLAB based controls algorithms into C codes, executable directly on EPICS process control computers (IOCs), was developed at the Paul Scherrer Institute (PSI). Based on this tool, several high level control applications were embedded into the IOCs, which are directly connected to the control system sensors and actuators. Such embedded applications have significantly reduced the network traffic, and thus the data handling latency, which increased the reliability of the control system. The paper concentrates on the most important components of the automated tool and the performance of MATLAB algorithms converted by this tool.  
poster icon Poster TUPHA020 [0.784 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-TUPHA020  
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THMPA09 MACUP (Material for data ACquisition - UPgrade): Project Focusing on DAQ Hardware Architecture Upgrades for SOLEIL ion, operation, hardware, controls 1330
 
  • G. Renaud, Y.-M. Abiven, F. Ta, Q.H. Tran, S. Zhang
    SOLEIL, Gif-sur-Yvette, France
  
  Since operation-startup more than 10 years ago, Synchrotron SOLEIL has chosen acquisition architectures that are mainly based on CompactPCI systems. The last few years there has however been an acceleration of obsolescence issues on the CPCI products and it has also been identified that this technology would become a bottleneck in terms of performance for new projects. The MACUP project was therefore created with two main objectives: maintaining the current facility operations by addressing the hardware obsolescence risks, all while searching for alternate high-performance solutions with better embedded processing capabilities to face new challenging requirements. One additional guideline for the project is to facilitate collaborative work for accelerator and beamline projects by evaluating and standardizing a limited set of technologies like the Xilinx ZYNQ SOC, VITA 57 FMC and μTCA standards. This paper describes the adopted methodologies and roadmap to drive this project.  
slides icon Slides THMPA09 [1.556 MB]  
poster icon Poster THMPA09 [0.678 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THMPA09  
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THPHA174 Preventing Run-Time Bugs at Compile-Time Using Advanced C++ ion, network, controls, status 1834
 
  • R. Neswold
    Fermilab, Batavia, Illinois, USA
  
  When writing software, we develop algorithms that tell the computer what to do at run-time. Our solutions are easier to understand and debug when they are properly modeled using class hierarchies, enumerations, and a well-factored API. Unfortunately, even with these design tools, we end up having to debug our programs at run-time. Worse still, debugging an embedded system changes its dynamics, making it tough to find and fix concurrency issues. This paper describes techniques using C++ to detect run-time bugs *at compile time*. A concurrency library, developed at Fermilab, is used for examples in illustrating these techniques.  
poster icon Poster THPHA174 [0.239 MB]  
DOI • reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2017-THPHA174  
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