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Nakagawa, H.

Paper Title Page
TUP070 Development of Spill Control System for the J-PARC Slow Extraction 245
 
  • S. Onuma, T. I. Ichikawa, K. Mochiki
    Tokyo City University, Tokyo
  • T. Adachi, A. Kiyomichi, R. Muto, H. Nakagawa, H. Sato, H. Someya, M. Tomizawa
    KEK, Ibaraki
  • K. Noda
    NIRS, Chiba-shi
 
  J-PARC (Japan Proton Accelerator Research Complex) is a new accelerator facility to produce MW-class high power proton beams. From the main ring high energy protons are extracted in a slow extracted mode for hadrons experiments. The slow extraction beam is required with as small ripple as possible to prevent pileup events in particle detectors or data acquisition systems. Based on preliminary experiments at HIMAC (Heavy Ion Medical Accelerator in Chiba) using a prototype signal processing board, we have developed a new signal processing board for the spill feedback control. The circuit board consists of three signal input ports for gate, spill intensity and residual beam intensity in the main ring, three signal output ports for spill control magnets, two DSPs (TMS320C6713) for the analysis of power spectrum and the spill feedback control, dual port memories, FPGAs and a LAN interface for remote control to change feedback parameters. Using this board, digital filtering, phase-shift processing, servo feedback control, real-time calculation of power spectrum density and adaptive control are examined.  
poster icon Poster  
THC005 The Implementation of the Software Framework in J-PARC/MLF 676
 
  • T. Nakatani, A. Arai, S. Harjo, Y. Inamura, T. Ito, R. K. Kajimoto
    JAEA/J-PARC, Tokai-Mura, Naka-Gun, Ibaraki-Ken
  • T. Aoyagi
    Japan Atomic Energy Agancy, Taito-ku Tokyo
  • T. Hosoya, M. Yonemura
    Ibaraki University, Hitachi, Ibaraki
  • R. Kadono, T. Morishima, S. Muto, O. Otomo, J. Suzuki, S. Torii, Y. Yasu
    KEK, Ibaraki
  • H. Nakagawa, T. Ohhara
    JAEA, Ibaraki-ken
 
  In the neutron scattering experiments, it is necessary to use many kinds of software components such as the data acquisition, equipment control, analysis and visualization. Additionally, in J-PARC/MLF, because the proton intensity will increase more and more, we will have to extend the capacity of the software to keep in the step. Therefore, the software is necessarily flexible and scalable for the various experiments and the enormous data (several tens of giga-bytes per hour). We have constructed the common software framework and then made many software components running on this software framework. Our software framework is based on Python which is an object oriented script language and the distributed network processing with XML messages over HTTP, for example the "RESTful" data acquisition and equipment control system. Through our software framework, not only the experimental users can seamlessly operate the neutron experimental instruments and analyze their acquired data but also the instrument scientists can coordinate the instruments and manage their configuration. In this presentation, we report the detailed implementation of our software framework.  
WEC006 The Accelerator Protection System Based on Embedded EPICS for J-PARC 406
 
  • H. Nakagawa, A. Akiyama, J.-I. Odagiri
    KEK, Ibaraki
  • Y. Kato
    JAEA/J-PARC, Tokai-Mura, Naka-Gun, Ibaraki-Ken
 
  There is the 4 output beam line at the MainRing(MR) in J-PARC. The Accelerator protection system (MPS-MR) watches the devices which deals with destination of the beam. Then, the heart for the logic judgment carries out the complicated logic treatment using FPGA (Virtex-4 FX). This FPGA takes in destination information of the beam, and the logical operation with trouble information is carried out to make an output. Then, the FPGA takes in the information on the destination of the beam using the LAN. In addition, information of the abnormal equipment which becomes the reason for the beam to be stopped is sent to OPI using the LAN. By giving PowerPC core to realize this communication function in the FPGA, LINUX+EPICS is operated on the PowerPC core. Though there are both logic processing unit and CPU on one element, because, the information transfer in high speed between logic processing unit and CPU is possible without requiring the complicated external wiring. In this reason, the system can be very efficiently constructed. This paper describes the detail of the design and the implementation, as well as the experiences of the system in the operation of the J-PARC MR.  
WEP070 Data Acquisition System of Beam Loss Monitors of the J-PARC Main Ring 537
 
  • S. Motohashi, M. Takagi
    Kanto Information Service (KIS), Accelerator Group, Ibaraki
  • D. A. Arakawa, Y. Hashimoto, N. Kamikubota, H. Nakagawa, J.-I. Odagiri, T. Toyama, S. Yamada, N. Yamamoto
    KEK, Ibaraki
 
  Beam loss monitors are essential diagnostic devices for the operation of J-PARC Main Ring, which aims at the acceleration of the world-highest-power proton beams. The data acquisition system of the beam loss monitors is required to measure the time structure of the output signal integrated during the acceleration cycle. The repetition rate of the measurement in the duration needs to reach at a level of tens of Hertz with time jitters less than a few milliseconds. In addition, the measured data must be accessible by the EPICS-based control system, which manages the whole accelerator control. In order to satisfy the requirement, a new type of Input / Output Controller (IOC), which runs Linux on a CPU module of FA-M3 Programmable Logic Controller (PLC), has been adopted. To execute the data acquisition, the CPU module functions with high speed data acquisition modules of FA-M3 on the PLC-bus. We found that the IOC could meet the requirements and the development and maintenance of the software for the IOC was considerably efficient.  
WEP076 Control of the J-PARC Slow Extraction Line Based on Embedded EPICS 549
 
  • M. Takagi
    Kanto Information Service (KIS), Accelerator Group, Ibaraki
  • N. Kamikubota, A. Kiyomichi, S. Murasugi, R. Muto, H. Nakagawa, J.-I. Odagiri, K. Okamura, Y. Shirakabe, M. Tomizawa, N. Yamamoto
    KEK, Ibaraki
 
  The J-PARC Main Ring supplies high energy proton beams to the hadron experiment facility through the slow extraction line. It comprised of a series of septa, staring from a pair of electrostatic septa (ESS) followed by magnetic septa, and some of those septa are movable by using stepping motors to adjust their positions for a better optics. In order to control the power supplies of the septa and the stepping motors, an EPICS-based control is implemented based on a new type of Input / Output Controller (IOC), which runs Linux on a CPU module of FA-M3 Programmable Logic Controller (PLC). The CPU functions with normal I/O modules of FA-M3 on the PLC-bus. The most remarkable feature of the control system is that we replaced ladder programs with EPICS sequencer programs for the efficiency of the software development and ease of maintenance. And we found that the new type of IOCs had worked without any serious troubles during the beam commissioning period, from Run#21(Jan.2009) through Run22(Feb.2009). This paper describes the details of the new IOC and its experiences in J-PARC operation including long term stability.  
THD005 Application of EPICS on F3RP61 to Accelerator Control 916
 
  • J.-I. Odagiri, S. Araki, K. Furukawa, N. Kamikubota, A. Kiyomichi, K. Mikawa, S. Murasugi, H. Nakagawa, T. T. Nakamura, S. Yamada, N. Yamamoto
    KEK, Ibaraki
  • K. Kameda, T. Natsui, H. Shiratsu
    Yokogawa, Tokyo
  • M. Komiyama
    RIKEN Nishina Center, Wako
  • S. Motohashi, M. Takagi
    Kanto Information Service (KIS), Accelerator Group, Ibaraki
  • N. Nagura
    Nippon Advanced Technology Co. Ltd., Ibaraki-prefecture
  • T. Nakamura
    MELCO SC, Tsukuba
  • A. Uchiyama
    SHI Accelerator Service ltd., Tokyo
 
  A new type of Input / Output Controller (IOC) has been developed based on F3RP61, a CPU module of FA-M3 Programmable Logic Controller (PLC). Since the CPU module runs Linux as its operating system, it takes no special effort to run EPICS IOC core program on the CPU module. With the aid of wide variety of I/O modules of FA-M3 PLC, the F3RP61-based IOC has various applications in accelerator control, such as magnet power supply control, monitoring interlock system, stepping motor control, data acquisition from beam monitors and so forth. The adoption of the new IOC makes the architecture of accelerator control systems simpler by unifying the two layers of front-end computers, i.e., the IOC layer and the PLC layer, into one layer. We found that the simplification of the control system architecture helps us to reduce the time and cost for the development and maintenance of the application software.