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Dedic, J.

Paper Title Page
TUC004 The White Rabbit Project 93
 
  • J. Serrano, P. Alvarez, M. Cattin, E. G. Cota, J. H. Lewis, P. M. Oliveira Fernandes Moreira, T. Wlostowski
    CERN, Geneva
  • R. Baer, T. Fleck, M. Kreider, C. Prados, S. Rauch
    GSI, Darmstadt
  • J. Dedic
    Cosylab, Ljubljana
  • G. Gaderer, P. Loschmidt
    Austrian Academy of Sciences, Wien
  
  Reliable, fast and deterministic transmission of control information in a network is a need for many distributed systems. One example is timing systems, where a reference frequency is used to accurately schedule time-critical messages. The White Rabbit (WR) project is a multi-laboratory and multi-company effort to bring together the best of the data transfer and timing worlds in a completely open design. It takes advantage of the latest developments for improving timing over Ethernet, such as IEEE 1588 (Precision Time Protocol) and Synchronous Ethernet. The presented approach aims for a general purpose, fieldbus-like transmission system, which provides deterministic data and timing (sub-ns accuracy and ps jitter) to around 1000 stations. It automatically compensates for fiber lengths in the order of 10 km. This paper describes the WR design goals and the specification used for the project. It goes on to describe the central component of the WR system structure - the WR switch - with theoretical considerations about the requirements. Finally, it presents real timing measurements for the first prototypes of WR hardware.  
WEP039 Timing System Upgrade for SNS 483
 
  • D. H. Thompson
    ORNL, Oak Ridge, Tennessee
  • D. Curry
    ORNL RAD, Oak Ridge, Tennessee
  • J. Dedic
    Cosylab, Ljubljana
  
  Funding: SNS is managed by UT-Battelle, LLC, under contract DE-AC05-00OR22725 for the U. S. Department of Energy

A timing system is a crucial subsystem of every accelerator, responsible for orchestrating the entire machine cycle by cycle. The current SNS timing system is based on the modified BNL solution which in turn is based on previous systems at other sites. The timing master is a collection of low functionality VME building blocks that are highly dependent on creative software to achieve the needed system functionality. The implementation technology of the whole system is backdated, making it impossible to build and maintain spares and boards for machine upgrades. At SNS we chose a roadmap which would allow a gradual upgrade of the timing system without having to redesign everything at once and yet provide a path for future modernization of the infrastructure. This paper presents progress on new timing master and receiver card, which will provide us with more flexible control and greater reliability by tremendously reducing the component count while still retaining compatibility with existing timing receiver units. The designs emphasize the use of FPGA technology in a way that simplifies the supporting software. The design of the system is a collaboration effort of ORNL and Cosylab.