Paper | Title | Page |
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TUPCF02 | Modeling the Fast Orbit Feedback Control System for APS Upgrade | 196 |
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Funding: Work supported by the U.S. Department of Energy, Office of Science, under Contract No. DE-AC02-06CH11357 The expected beam sizes for APS Upgrade are in the order of 4 microns for both planes. Orbit stabilization to 10% of the beam size with such small cross-sections requires pushing the state of the art in fast orbit feedback control, both in the spatial domain and in dynamical performance; the latter being the subject of this paper. In this paper, we begin to study possible performance benefits of moving beyond the classic PID regulator to more sophisticated methods in control theory that take advantage of a-priori knowledge of orbit motion spectra and system non-linearities. A reliable model is required for this process. Before developing a predictive model for the APS Upgrade, the system identification methodology is tested and validated against the present APS storage ring. This paper presents the system identification process, measurement results, and discusses model validation. |
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DOI • | reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2017-TUPCF02 | |
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TUPCF04 | Feedback Controller Development for the APS-MBA Upgrade | 203 |
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The Advanced Photon Source (APS) is currently in the preliminary design phase for the multi-bend achromat (MBA) lattice upgrade. Broadband Root Mean Square (rms) orbit motion should stay within 10% of a beam cross-section of the order 4μm x 4μm rms at the insertion device source-points. In order to meet these stringent AC beam stability requirements, a new orbit feedback system is under development and is being tested on the existing APS storage ring. The controller prototype uses Commercial Off-The-Shelf (COTS) hardware that has both high-performance Xilinx Field-Programmable Gate Array (FPGA) and two high-performance Texas-Instruments Digital Signal Processors (DSP) onboard. In this paper, we will discuss the rationale for a combined DSP/FPGA architecture and how functions are allocated. We then present the FPGA architecture and the results of using Infinite Impulse Response (IIR) filtering to mitigate Beam Position Monitor (BPM) switching noise and aliasing. | ||
DOI • | reference for this paper ※ https://doi.org/10.18429/JACoW-IBIC2017-TUPCF04 | |
Export • | reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml) | |