Author: Verstovsek, I.     [Verstovšek, I.]
Paper Title Page
MOPGF125 The General Interlock System (GIS) for FAIR 374
 
  • F. Ameil, C. Betz
    GSI, Darmstadt, Germany
  • G. Cuk, I. Verstovšek
    Cosylab, Ljubljana, Slovenia
  
  The In­ter­lock Sys­tem for FAIR named Gen­eral In­ter­lock Sys­tem (GIS) is part of the Ma­chine Pro­tec­tion Sys­tem which pro­tects the ac­cel­er­a­tor from dam­age by mis­led beams. The GIS col­lects var­i­ous In­ter­lock sources hard­ware sig­nals from up to 60 dis­trib­uted re­mote I/O sta­tions through PROFINET to a cen­tral PLC CPU. Thus a bit-field is build and sent to the in­ter­lock proces­sor via a sim­ple Eth­er­net point-to-point con­nec­tion. Ad­di­tional soft­ware In­ter­lock sources can be picked up by the In­ter­lock Proces­sor via UDP/IP pro­to­col. The In­ter­lock Sys­tem for FAIR pro­ject was di­vided into 2 de­vel­op­ment phases. Phase A con­tains the in­ter­lock sig­nal gath­er­ing (HW and SW) and a sta­tus viewer. Phase B en­tails the fully func­tional in­ter­lock logic (sup­port for dy­namic con­fig­u­ra­tion), in­ter­face with Tim­ing Sys­tem, in­ter­lock sig­nal ac­knowl­edg­ing, in­ter­lock sig­nal mask­ing, archiv­ing and log­ging. The re­al­iza­tion of the phase A will be pre­sented in this paper.  
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