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TY - CONF AU - Ameil, F. AU - Betz, C. AU - Cuk, G. AU - Verstovšek, I. ED - Corvetti, Lou ED - Riches, Kathleen ED - Schaa, Volker RW TI - The General Interlock System (GIS) for FAIR J2 - Proc. of ICALEPCS2015, Melbourne, Australia, 17-23 October 2015 C1 - Melbourne, Australia T2 - International Conference on Accelerator and Large Experimental Physics Control Systems T3 - 15 LA - english AB - The Interlock System for FAIR named General Interlock System (GIS) is part of the Machine Protection System which protects the accelerator from damage by misled beams. The GIS collects various Interlock sources hardware signals from up to 60 distributed remote I/O stations through PROFINET to a central PLC CPU. Thus a bit-field is build and sent to the interlock processor via a simple Ethernet point-to-point connection. Additional software Interlock sources can be picked up by the Interlock Processor via UDP/IP protocol. The Interlock System for FAIR project was divided into 2 development phases. Phase A contains the interlock signal gathering (HW and SW) and a status viewer. Phase B entails the fully functional interlock logic (support for dynamic configuration), interface with Timing System, interlock signal acknowledging, interlock signal masking, archiving and logging. The realization of the phase A will be presented in this paper. PB - JACoW CP - Geneva, Switzerland SP - 374 EP - 377 KW - hardware KW - software KW - PLC KW - pick-up KW - network DA - 2015/12 PY - 2015 SN - 978-3-95450-148-9 DO - 10.18429/JACoW-ICALEPCS2015-MOPGF125 UR - http://jacow.org/icalepcs2015/papers/mopgf125.pdf ER -