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The General Interlock System (GIS) for FAIR |
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- F. Ameil, C. Betz
GSI, Darmstadt, Germany
- G. Cuk, I. Verstovšek
Cosylab, Ljubljana, Slovenia
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The Interlock System for FAIR named General Interlock System (GIS) is part of the Machine Protection System which protects the accelerator from damage by misled beams. The GIS collects various Interlock sources hardware signals from up to 60 distributed remote I/O stations through PROFINET to a central PLC CPU. Thus a bit-field is build and sent to the interlock processor via a simple Ethernet point-to-point connection. Additional software Interlock sources can be picked up by the Interlock Processor via UDP/IP protocol. The Interlock System for FAIR project was divided into 2 development phases. Phase A contains the interlock signal gathering (HW and SW) and a status viewer. Phase B entails the fully functional interlock logic (support for dynamic configuration), interface with Timing System, interlock signal acknowledging, interlock signal masking, archiving and logging. The realization of the phase A will be presented in this paper.
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