ICALEPCS2013 - List of Authors (Rehlich, K.)

Paper

Title

Page

The Case of MTCA.4: Managing the Introduction of a New Crate Standard at Large Scale Facilities and Beyond

285

T. Walter, F. Ludwig, K. Rehlich, H. Schlarb
DESY, Hamburg, Germany

The demands on hardware for control and data acquisition at large-scale research organizations have increased considerably in recent years. In response, modular systems based on the new MTCA.4 standard, jointly developed by large Public Research Organizations and industrial electronics manufacturers, have pushed the boundary of system performance in terms of analog/digital data processing performance, remote management capabilities, timing stability, signal integrity, redundancy and maintainability. Whereas such public-private collaborations are not entirely new, novel instruments are in order to test the acceptance of the MTCA.4 standard beyond the physics community, identify gaps in the technology portfolio and align collaborative R&D programs accordingly. We describe the ongoing implementation of a time-limited validation project as means towards this end, highlight the challenges encountered so far and present solutions for a sustainable division of labor along the industry value chain.

TUMIB09

jddd: A Tool for Operators and Experts to Design Control System Panels

544

E. Sombrowski, A. Petrosyan, K. Rehlich, W. Schütte
DESY, Hamburg, Germany

jddd, a graphical tool for control system panel design, has been developed at DESY to allow machine operators and experts the design of complex panels. No knowledge of a programming language nor compiling steps are required to generate highly dynamic panels with the jddd editor. After 5 years of development and implementing requirements for DESY-specific accelerator operations, jddd has become mature and is increasingly used at DESY. The focus meanwhile has changed from pure feature development to new tasks as archiving/managing a huge number of control panels, finding panel dependencies, automatic refactoring of panel names, book keeping and evaluation of panel usage and collecting Java exception messages in an automatic manner. Therefore technologies of the existing control system infrastructure like Servlets, JMS, Lucene, SQL, SVN are used. The concepts and technologies to further improve the quality and robustness of the tool are presented in this paper.

Slides TUMIB09 [0.811 MB]

Poster TUMIB09 [1.331 MB]

THCOBB02

Recent Hardware and Software Achievements for the European XFEL

K. Rehlich
DESY, Hamburg, Germany

The European XFEL will deliver photon beams to several users in parallel. In the first phase 5 beam lines for experiments are foreseen. A complex bunch distribution and protection system was developed to handle a huge number of bunches. Furthermore, high performance hardware based on MicroTCA together with efficient software to cope with the data rates, have been demonstrated at FLASH. FLASH operates since many years as a FEL with wavelengths down to 4nm. It is an ideal testbed for new hardware and software to be used later in the XFEL. This paper describes the architecture of the layered system with FPGA feedbacks, synchronized front-end hardware / software and data processing up to slow feedbacks running on central servers.

Slides THCOBB02 [2.544 MB]

Paper	Title	Page
MOPPC081	The Case of MTCA.4: Managing the Introduction of a New Crate Standard at Large Scale Facilities and Beyond	285
	T. Walter, F. Ludwig, K. Rehlich, H. Schlarb DESY, Hamburg, Germany
	The demands on hardware for control and data acquisition at large-scale research organizations have increased considerably in recent years. In response, modular systems based on the new MTCA.4 standard, jointly developed by large Public Research Organizations and industrial electronics manufacturers, have pushed the boundary of system performance in terms of analog/digital data processing performance, remote management capabilities, timing stability, signal integrity, redundancy and maintainability. Whereas such public-private collaborations are not entirely new, novel instruments are in order to test the acceptance of the MTCA.4 standard beyond the physics community, identify gaps in the technology portfolio and align collaborative R&D programs accordingly. We describe the ongoing implementation of a time-limited validation project as means towards this end, highlight the challenges encountered so far and present solutions for a sustainable division of labor along the industry value chain.

TUMIB09	jddd: A Tool for Operators and Experts to Design Control System Panels	544
	E. Sombrowski, A. Petrosyan, K. Rehlich, W. Schütte DESY, Hamburg, Germany
	jddd, a graphical tool for control system panel design, has been developed at DESY to allow machine operators and experts the design of complex panels. No knowledge of a programming language nor compiling steps are required to generate highly dynamic panels with the jddd editor. After 5 years of development and implementing requirements for DESY-specific accelerator operations, jddd has become mature and is increasingly used at DESY. The focus meanwhile has changed from pure feature development to new tasks as archiving/managing a huge number of control panels, finding panel dependencies, automatic refactoring of panel names, book keeping and evaluation of panel usage and collecting Java exception messages in an automatic manner. Therefore technologies of the existing control system infrastructure like Servlets, JMS, Lucene, SQL, SVN are used. The concepts and technologies to further improve the quality and robustness of the tool are presented in this paper.
	Slides TUMIB09 [0.811 MB]
	Poster TUMIB09 [1.331 MB]

THCOBB02	Recent Hardware and Software Achievements for the European XFEL
	K. Rehlich DESY, Hamburg, Germany
	The European XFEL will deliver photon beams to several users in parallel. In the first phase 5 beam lines for experiments are foreseen. A complex bunch distribution and protection system was developed to handle a huge number of bunches. Furthermore, high performance hardware based on MicroTCA together with efficient software to cope with the data rates, have been demonstrated at FLASH. FLASH operates since many years as a FEL with wavelengths down to 4nm. It is an ideal testbed for new hardware and software to be used later in the XFEL. This paper describes the architecture of the layered system with FPGA feedbacks, synchronized front-end hardware / software and data processing up to slow feedbacks running on central servers.
	Slides THCOBB02 [2.544 MB]