ICALEPCS2013 - List of Authors (Jaussi, M.)

Paper	Title	Page
TUPPC116	Cheburashka: A Tool for Consistent Memory Map Configuration Across Hardware and Software	848
	A. Rey, A.C. Butterworth, F. Dubouchet, M. Jaussi, T.E. Levens, J.C. Molendijk, A.V. Pashnin CERN, Geneva, Switzerland
	The memory map of a hardware module is defined by the designer at the moment when the firmware is specified. It is then used by software developers to define device drivers and front-end software classes. Maintaining consistency between hardware and its software is critical. In addition, the manual process of writing VHDL firmware on one side and the C++ software on the other is labour-intensive and error-prone. Cheburashka* is a software tool which eases this process. From a unique declaration of the memory map, created using the tool’s graphical editor, it allows to generate the memory map VHDL package, the Linux device driver configuration for the front-end computer, and a FESA class for debugging. An additional tool, GENA, is being used to automatically create all required VHDL code to build the associated register control block. These tools are now used by the hardware and software teams for the design of all new interfaces from FPGAs to VME or on-board DSPs in the context of the extensive program of development and renovation being undertaken in the CERN injector chain during LS1. Several VME modules and their software have already been deployed and used in the SPS. () Cheburashka is developed in the RF group at CERN ()FESA is an acronym for Front End Software Architecture, developped at CERN (*)LS1 : LHC Long Shutdown 1, from 2013 to 2014

Paper

Title

Page

Cheburashka: A Tool for Consistent Memory Map Configuration Across Hardware and Software

848

A. Rey, A.C. Butterworth, F. Dubouchet, M. Jaussi, T.E. Levens, J.C. Molendijk, A.V. Pashnin
CERN, Geneva, Switzerland

The memory map of a hardware module is defined by the designer at the moment when the firmware is specified. It is then used by software developers to define device drivers and front-end software classes. Maintaining consistency between hardware and its software is critical. In addition, the manual process of writing VHDL firmware on one side and the C++ software on the other is labour-intensive and error-prone. Cheburashka* is a software tool which eases this process. From a unique declaration of the memory map, created using the tool’s graphical editor, it allows to generate the memory map VHDL package, the Linux device driver configuration for the front-end computer, and a FESA** class for debugging. An additional tool, GENA, is being used to automatically create all required VHDL code to build the associated register control block. These tools are now used by the hardware and software teams for the design of all new interfaces from FPGAs to VME or on-board DSPs in the context of the extensive program of development and renovation being undertaken in the CERN injector chain during LS1***. Several VME modules and their software have already been deployed and used in the SPS.
(*) Cheburashka is developed in the RF group at CERN
(**)FESA is an acronym for Front End Software Architecture, developped at CERN
(***)LS1 : LHC Long Shutdown 1, from 2013 to 2014