ICALEPCS2013 - List of Authors (Claesson, N.)

Paper

Title

Page

EPICS Data Acquisition Device Support

707

V.A. Isaev, N. Claesson
Cosylab, Ljubljana, Slovenia
M. Pleško, K. Žagar
COBIK, Solkan, Slovenia

A large number of devices offer a similar kind of capabilities. For example, data acquisition all offer sampling at some rate. If each such device were to have a different interface, engineers using them would need to be familiar with each device specifically, inhibiting transfer of know-how from working with one device to another and increasing the chance of engineering errors due to a miscomprehension or incorrect assumptions. In the Nominal Device Model (NDM) model, we propose to standardize the EPICS interface of the analog and digital input and output devices, and image acquisition devices. The model describes an input/output device which can have digital or analog channels, where channels can be configured for output or input. Channels can be organized in groups that have common parameters. NDM is implemented as EPICS Nominal Device Support library (NDS). It provides a C++ interface to developers of device-specific drivers. NDS itself inherits well-known asynPortDriver. NDS hides from the developer all the complexity of the communication with asynDriver and allows to focus on the business logic of the device itself.

Poster TUPPC059 [0.371 MB]

THPPC102

Comparison of Synchronization Layers for Design of Timing Systems

1296

A. Aulin Söderqvist, N. Claesson, J. Neves Rodrigues
Lund University, Lund, Sweden
J. Dedič, R. Štefanič, R. Tavčar
Cosylab, Ljubljana, Slovenia

Two synchronization layers for timing systems in large experimental physics control systems are compared. White Rabbit (WR), which is an emerging standard, is compared against the well-established event based approach. Several typical timing system services have been implemented on an FPGA using WR to explore its concepts and architecture, which is fundamentally different from an event based. Both timing system synchronization layers were evaluated based on typical requirements of current accelerator projects and with regard to other parameters such as scalability. The proposed design methodology demonstrates how WR can be deployed in future accelerator projects.

Poster THPPC102 [1.796 MB]

Paper	Title	Page
TUPPC059	EPICS Data Acquisition Device Support	707
	V.A. Isaev, N. Claesson Cosylab, Ljubljana, Slovenia M. Pleško, K. Žagar COBIK, Solkan, Slovenia
	A large number of devices offer a similar kind of capabilities. For example, data acquisition all offer sampling at some rate. If each such device were to have a different interface, engineers using them would need to be familiar with each device specifically, inhibiting transfer of know-how from working with one device to another and increasing the chance of engineering errors due to a miscomprehension or incorrect assumptions. In the Nominal Device Model (NDM) model, we propose to standardize the EPICS interface of the analog and digital input and output devices, and image acquisition devices. The model describes an input/output device which can have digital or analog channels, where channels can be configured for output or input. Channels can be organized in groups that have common parameters. NDM is implemented as EPICS Nominal Device Support library (NDS). It provides a C++ interface to developers of device-specific drivers. NDS itself inherits well-known asynPortDriver. NDS hides from the developer all the complexity of the communication with asynDriver and allows to focus on the business logic of the device itself.
	Poster TUPPC059 [0.371 MB]

THPPC102	Comparison of Synchronization Layers for Design of Timing Systems	1296
	A. Aulin Söderqvist, N. Claesson, J. Neves Rodrigues Lund University, Lund, Sweden J. Dedič, R. Štefanič, R. Tavčar Cosylab, Ljubljana, Slovenia
	Two synchronization layers for timing systems in large experimental physics control systems are compared. White Rabbit (WR), which is an emerging standard, is compared against the well-established event based approach. Several typical timing system services have been implemented on an FPGA using WR to explore its concepts and architecture, which is fundamentally different from an event based. Both timing system synchronization layers were evaluated based on typical requirements of current accelerator projects and with regard to other parameters such as scalability. The proposed design methodology demonstrates how WR can be deployed in future accelerator projects.
	Poster THPPC102 [1.796 MB]