Paper |
Title |
Page |
MOPPC029 |
Internal Post Operation Check System for Kicker Magnet Current Waveforms Surveillance |
131 |
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- N. Magnin, E. Carlier, B. Goddard, V. Mertens, J.A. Uythoven
CERN, Geneva, Switzerland
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A software framework, called Internal Post Operation Check (IPOC), has been developed to acquire and analyse kicker magnet current waveforms. It was initially aimed at performing the surveillance of LHC beam dumping system (LBDS) extraction and dilution kicker current waveforms and was subsequently also deployed on various other kicker systems at CERN. It has been implemented using the Front-End Software Architecture (FESA) framework, and uses many CERN control services. It provides a common interface to various off-the-shelf digitiser cards, allowing a transparent integration of new digitiser types into the system. The waveform analysis algorithms are provided as external plug-in libraries, leaving their specific implementation to the kicker system experts. The general architecture of the IPOC system is presented in this paper, along with its integration within the control environment at CERN. Some application examples are provided, including the surveillance of the LBDS kicker currents and trigger synchronisation, and a closed-loop configuration to guarantee constant switching characteristics of high voltage thyratron switches.
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Poster MOPPC029 [0.435 MB]
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MOPPC064 |
A New Spark Detection System for the Electrostatic Septa of the SPS North (Experimental) Area |
246 |
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- R.A. Barlow, B. Balhan, J. Borburgh, E. Carlier, C. Chanavat, T. Fowler, B. Pinget
CERN, Geneva, Switzerland
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Electrostatic septa (ZS) are used in the extraction of the particle beams from the CERN SPS to the North Area experimental zone. These septa employ high electric fields, generated from a 300 kV power supply, and are particularly prone to internal sparking around the cathode structure. This sparking degrades the electric field quality, consequently affecting the extracted beam, vacuum and equipment performance. To mitigate these effects, a Spark Detection System (SDS) has been realised, which is based on an industrial SIEMENS S7-400 programmable logic controller and deported Boolean processors modules interfaced through a PROFINET fieldbus. The SDS interlock logic uses a moving average spark rate count to determine if the ZS performance is acceptable. Below a certain spark rate it is probable that the ZS septa tank vacuum can recover, thus avoiding transition into a state where rapid degradation would occur. Above this level an interlock is raised and the high voltage is switched off. Additionally, all spark signals acquired by the SDS are sent to a front-end computer to allow further analysis such as calculation of spark rates and production of statistical data.
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Poster MOPPC064 [0.366 MB]
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MOPPC066 |
Reliability Analysis of the LHC Beam Dumping System Taking into Account the Operational Experience during LHC Run 1 |
250 |
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- R. Filippini, E. Carlier, N. Magnin, J.A. Uythoven
CERN, Geneva, Switzerland
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The LHC beam dumping system operated reliably during the Run 1 period of the LHC (2009 – 2013). As expected, there were a number of internal failures of the beam dumping system which, because of in-built safety features, resulted in safe removal of the particle beams from the machine. These failures (i.e. "false" beam dumps) have been appointed to the different failure modes and are compared to the predictions made by a reliability model established before the start of LHC operation. A statistically significant difference between model and failure data identifies those beam dumping system components that may have unduly impacted on the LHC availability and safety or might have been out of the scope of the initial model. An updated model of the beam dumping system reliability is presented, taking into account the experimental data presented and the foreseen system changes to be made in the 2013 – 2014 LHC shutdown.
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Poster MOPPC066 [1.554 MB]
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MOPPC068 |
Operational Experience with a PLC Based Positioning System for a LHC Extraction Protection Element |
254 |
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- C. Boucly, J. Borburgh, C. Bracco, E. Carlier, N. Magnin, N. Voumard
CERN, Geneva, Switzerland
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The LHC Beam Dumping System (LBDS) nominally dumps the beam synchronously with the passage of the particle free beam abort gap at the beam dump extraction kickers. In the case of an asynchronous beam dump, an absorber element protects the machine aperture. This is a single sided collimator (TCDQ), positioned close to the beam, which has to follow the beam position and beam size during the energy ramp. The TCDQ positioning control is implemented within a SIEMENS S7-300 Programmable Logic Controller (PLC). A positioning accuracy better than 30 μm is achieved through a PID based servo algorithm. Errors due to a wrong position of the absorber w.r.t. the beam energy and size generates interlock conditions to the LHC machine protection system. Additionally, the correct position of the TCDQ w.r.t. the beam position in the extraction region is cross-checked after each dump by the LBDS eXternal Post Operational Check (XPOC). This paper presents the experience gained during LHC Run 1 and describes improvements that will be applied during the LHC shutdown 2013 – 2014.
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Poster MOPPC068 [3.381 MB]
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THPPC060 |
A PXI-Based Low Level Control for the Fast Pulsed Magnets in the CERN PS Complex |
1205 |
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- J. Schipper, E. Carlier, T. Fowler, T. Gharsa
CERN, Geneva, Switzerland
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Fast pulsed magnet (kicker) systems are used for beam injection and extraction in the CERN PS complex. A novel approach, based on off-the-shelf PXI components, has been used for the consolidation of the low level part of their control system. Typical functionalities required like interlocking, equipment state control, thyratron drift stabilisation and protection, short circuit detection in magnets and transmission lines, pulsed signal acquisition and fine timing have been successfully integrated within a PXI controller. The controller comprises a National Instruments NI PXI-810x RT real time processor, a multifunctional RIO module including a Virtex-5 LX30 FPGA, a 1 GS/s digitiser and a digital delay module with 1 ns resolution. National Instruments LabVIEW development tools have been used to develop the embedded real time software as well as FPGA configuration and expert application programs. The integration within the CERN controls environment is performed using the Rapid Application Development Environment (RADE) software tools, developed at CERN.
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Poster THPPC060 [0.887 MB]
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