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EPICS

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MOVNB01 Advanced Modular Oscilloscopes and Digitizers Optimized for Accelerator Applications controls, monitoring, instrumentation 63
 
  • L. Shaw, C.D. Ziomek
    ZTEC Instruments, Albuquerque
 
 

Modular oscilloscopes and digitizers, including those with embedded EPICS IOCs, provide powerful off-the-shelf solutions for accelerator controls and beamline data acquisition applications requiring fast sampling, high resolution and/or tight multi-channel synchronization. This presentation discusses features and capabilities of EPICS and non-EPICS LXI, VXI, PXI and PCI oscilloscopes and digitizers as they specifically relate to accelerator and beamline applications. Modular oscilloscopes and digitizers with on-board DSP and FPGAs provide the advanced waveform acquisition and analysis capabilities of benchtop instruments with the size and channel-density advantages of modular instruments. Instruments with on-board processing, such as those from ZTEC Instruments, enable real-time waveform math and waveform parameter analysis. Advanced triggering and multiple acquisition modes are other features found on some of today’s advanced modular instruments. Furthermore, instruments with embedded EPICS IOCs save users the time and money of developing their own EPICS drivers and display panels. Examples of specific accelerator applications using advanced modular instruments will be presented.

 

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TUVNB01 COTS Technology for High Energy Physics Instrumentation controls, instrumentation, diagnostics, status 84
 
  • M.M. Ravindran, J.T. Truchard
    National Instruments, Austin
 
 

Since 1976, National Instruments (NI) has taken off-the-shelf semiconductor and computing technology and applied it to measurement, diagnostics and instrumentation needs. NI leverages the rapid technological advancement of the semiconductor and computer industry, while retaining the flexibility and ensuring interoperability between HW & SW. This technical session will focus on the various models of computation, multicore technology applied to measurement and diagnostic needs, communication protocols, timing and synchronization, and FPGA designed-in to meet custom needs. Additionally we will see examples of Graphical System Design being applied at CERN, Max Planck, LANL, ESO and how COTS HW & SW technologies can be used to solve instrumentation needs.

 

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TUPSM027 New Beam Monitoring Instrumentation at ATF2, KEK controls, monitoring, quadrupole, alignment 173
 
  • E. A. Medvedko, R.G. Johnson, S.R. Smith, G.R. White
    SLAC, Menlo Park, California
 
 

A new stripline beam position monitoring (BPM) readout and processing system was installed and successfully tested over a two-week period at the Accelerator Test Facility 2 (ATF2), in KEK, Japan during February 2010. The core analog processing board used in the system is a duplicate of that developed for, and in use at, the Linac Coherent Light Source (LCLS) at SLAC. The digitization, processing and control front-end were custom designed for ATF2 using a 14-bit 100-MHz VME digitizer and an EPICS Input/Output Controller (IOC) running on the VME controller. Control of the analog boards is via EPICS, which controls a serial-over-TCP/IP port server. Hardware for the readout of up to 14 BPMs with 3 spare analog boards was delivered. The goal of this installation was to provide ~<10 micron resolution, non-charge-dependent readout of the ATF2 electron beam with long-term gain stability compensation. These criteria were tested and successfully met. This design was found to be highly effective and to have many advantages, especially that it required minimal installation effort at ATF2.

 
TUPSM064 An FPGA-based Bunch-by-Bunch Tune Measurement System for the APS Storage Ring controls 315
 
  • C. Yao, Y.-C. Chae
    ANL, Argonne
  • W.E. Norum
    LBNL, Berkeley, California
 
 

A bunch-by-bunch tune measurement system is a very powerful tool for beam diagnostics and machine studies. It can be applied to such machine physics studies as characterization of transverse impedance, observation and identification of coupled-mode instabilities, and electron cloud effects. We developed an FPGA-based bunch-by-bunch tune measurement system that excites a set of driven bunches with a frequency sweep signal, samples a set of monitored bunches, and extracts amplitude and phase information from sampled data using digital demodulation method. We report its hardware and software design, performance, and recent experimental results on the APS storage ring beam.

 
TUPSM083 The LCLS Timing Event System linac, controls, undulator, diagnostics 379
 
  • J.E. Dusatko, S. Allison, J. Browne, P. Krejcik
    SLAC, Menlo Park, California
 
 

The Linac Coherent Light Source requires precision timing trigger signals for various accelerator diagnostics and controls at SLAC-NAL. A new timing system has been developed that meets these requirements. This system is based on COTS hardware with a mixture of custom-designed units. An added challenge has been the requirement that the LCLS Timing System must co-exist and “know” about the existing SLC Timing System. This paper describes the architecture, construction and performance of the LCLS timing event system.

 
TUPSM095 Multi-Channel Magnet Power-Supply Ramp Controller for the IUCEEM ALPHA Synchrotron/Storage Ring with Channel Access controls, power-supply, electron, storage-ring 425
 
  • S. Cohen
    Bira, Albuquerque, New Mexico
  • G.W. East, R.W. Ellis
    IUCMB, Bloomington, Indiana
 
 

A four-channel magnet-power-supply ramp controller has been designed and deployed at the new ALPHA (Advanced Electron Photon Facility) at the IUCMB (Indiana University Center for Matter and Beams). The first application is a power-supply controller; however, the system is a versatile arbitrary voltage-waveform generator with full DAQ (data acquisition) capabilities that can be used in a variety of beam instrumentation settings. The real-time controller can generate four arbitrary, independently-triggerable ramp profiles. A normalized wave-form array is encoded as a Process Variable array and is uploaded and stored by the real-time controller as required. Each ramp array is clocked out to a 16-bit DAC (Digital to Analog Converter) via a DMA FIFO and built-in FPGA. The duration of the waveform is programmable with a minimum time resolution of 20 usec between profile values. Four bipolar DACs have an output range of ± 10V. Eight digital I/O control bits are allocated for each control channel. Typically, these bits are used to monitor and control the power-supply operational state. The control-system interface uses the EPICS Channel-Access server accessible on Labview RT 2009.