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| THPC122 |
Digital Signal Processing for the Multi-bunch LHC Transverse Feedback System
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3269 |
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- W. Höfle, P. Baudrenghien, G. Kotzian, V. Rossi
CERN, Geneva
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For the LHC a VME card has been developed that contains all functionalities for transverse damping, diagnostics and controlled bunch by bunch excitation. It receives the normalized bunch by bunch position from two pick-ups via Gigabit Serial Links (SERDES). A Stratix II FPGA is responsible for resynchronising the two data streams to the bunch-synchronous clock domain (40.08 MHz) and then applying all the digital signal processing: In addition to the classic functionalities (gain balance, rejection of closed orbit, pick-up combinations, one-turn delay) it contains 3-turn Hilbert filters for phase adjustment with a single pick-up scheme, a phase equalizer to correct for the non-linear phase response of the power amplifier and an interpolator to double the processing frequency followed by a low-pass filter to precisely control the bandwidth. Using two clock domains in the FPGA the phase of the feedback loop can be adjusted with a resolution of 10 ps. Built-in diagnostic memory (observation and post-mortem) and excitation memory for setting-up are also included. The card receives functions to continuously adjust its parameters as required during injection, ramping and physics.
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| THPC121 |
LHC Transverse Feedback System and its Hardware Commissioning
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3266 |
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- W. Höfle, P. Baudrenghien, F. Killing, Y. A. Kojevnikov, G. Kotzian, R. Louwerse, E. Montesinos, V. Rossi, M. Schokker, E. Thepenier, D. Valuch
CERN, Geneva
- E. V. Gorbachev, N. I. Lebedev, A. A. Makarov, S. Rubtsun, V. Zhabitsky
JINR, Dubna, Moscow Region
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A powerful transverse feedback system ('damper') has been installed in LHC. It will stabilise coupled bunch instabilities in a frequency range from 3 kHz to 20 MHz and at the same time damp injection oscillations originating from steering errors and injection kicker ripple. The transverse damper can also be used as an exciter for purposes of abort gap cleaning or tune measurement. The power and low-level systems layout are described along with results from the hardware commissioning. The achieved performance is compared with earlier predictions and requirements for injection damping and instability control. Requirements and first measurements of the performance of the low-level system are summarized. The chosen approach for the low-level system using advanced FPGA technology is very flexible allowing implementation of future upgrades of the signal processing without changing the hardware.
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