• M. Liu, D.K. Liu, C.X. Yin, L.Y. Zhao
  SINAP, Shanghai

Currently, the real-time data transfer system is widely implemented in the accelerator control system. If timing system and real-time data transfer system could be combined into one uniform system, it would be convenient to build distributed feedback system, fast interlock system and so on. So, a new timing system, the real-time synchronized data bus is developed to realize this idea. The architecture of the system and the hardware prototype design are introduced in the paper. The data exchange mechanism and system specification, including timing trigger synchronization accuracy, timing jitter relative to RF clock, data transfer rate and latency are described in detail. Redundant topology structure and fiber length compensation are specially considered. In the end, the results of testing in lab are presented.

• L.R. Shen, D.K. Liu
  SINAP, Shanghai

SSRF control system is a hierarchical standard accelerator control system based on EPICS. The VME 64X system, special embedded controller and PLCs are used for low level devices control or interlocks system. Using a uniform 1000Base-T backbone redundancy control network instead of field bus for mostly device controller with VLAN technique adopted, and integrate with EPICS using soft IOC. Digital technology such as digital power supply control system, new event timing system and digital phase control system are used and also integrated with some embedded EPICS IOC. An uniform System development and run time environment of hardware and software is adopted at the whole process. The high level physical application environment using MatLab 2007a with Accelerator Toolbox (AT) & middle layer with MatLab CA (Channel Access) connected component MCA/LabCA. The high level physical application can be integrated with the control system easily and conveniently. With the SSRF centre database, an enhanced distributed archive engine based on RDBS with native XML data type is been testing.