PCaPAC2022 - List of Authors (Rauch, S.)

Paper	Title	Page
THP15	Next Generation GSI/FAIR Scalable Control Unit: Lessons Learned from 10 Years in the Field	76
	K. Lüghausen, M. Dziewiecki, K. Kaiser, G.M. May, S. Rauch, M. Thieme GSI, Darmstadt, Germany
	The end-of-life of many components brought the need for a redesign of our main Control System Front-End - the SCU (Scaleable Control Unit). It was a chance to make improvements and use more powerful state-of-the-art core components. This included a new Arria 10 FPGA and a completely redesigned housekeeping circuit based on an AVR microcontroller. Further, the project was cleaned by removing unused components and features. Main frame conditions stay fixed for backward compatibility, like the mechanical form factor or the 16-bit parallel bus. Majority of gateware and firmware could be reused and just some adaptations for the new FPGA were needed. Nevertheless, providing continuous compatibility with legacy peripherals needed a substantial effort.
	Poster THP15 [27.393 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-PCaPAC2022-THP15
About •	Received ※ 30 September 2022 — Revised ※ 06 October 2022 — Accepted ※ 01 February 2023 — Issue date ※ 18 February 2023
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Next Generation GSI/FAIR Scalable Control Unit: Lessons Learned from 10 Years in the Field

76

K. Lüghausen, M. Dziewiecki, K. Kaiser, G.M. May, S. Rauch, M. Thieme
GSI, Darmstadt, Germany

The end-of-life of many components brought the need for a redesign of our main Control System Front-End - the SCU (Scaleable Control Unit). It was a chance to make improvements and use more powerful state-of-the-art core components. This included a new Arria 10 FPGA and a completely redesigned housekeeping circuit based on an AVR microcontroller. Further, the project was cleaned by removing unused components and features. Main frame conditions stay fixed for backward compatibility, like the mechanical form factor or the 16-bit parallel bus. Majority of gateware and firmware could be reused and just some adaptations for the new FPGA were needed. Nevertheless, providing continuous compatibility with legacy peripherals needed a substantial effort.

Poster THP15 [27.393 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-PCaPAC2022-THP15

About •

Received ※ 30 September 2022 — Revised ※ 06 October 2022 — Accepted ※ 01 February 2023 — Issue date ※ 18 February 2023

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)