The Joint Accelerator Conferences Website (JACoW) is an international collaboration that publishes the proceedings of accelerator conferences held around the world.
TY - CONF AU - Christian, G.B. AU - Blaskovic Kraljevic, N. AU - Bodenstein, R.M. AU - Bromwich, T. AU - Burrows, P. AU - Perry, C. AU - Ramjiawan, R.L. AU - Roberts, J. ED - Schaa, Volker RW TI - A Fast, Custom FPGA-Based Signal Processor and Its Applications to Intra-Train Beam Stabilisation J2 - Proc. of PCaPAC2016, Campinas, Brazil, October 2528, 2016 C1 - Campinas, Brazil T2 - International Workshop on Personal Computers and Particle Accelerator Controls T3 - 11 LA - english AB - A custom 9-channel feedback controller has been developed for low-latency applications in beam-based stabilisation. Fast 14-bit ADCs and DACs are used for high-resolution signal conversion and a Xilinx Virtex-5 FPGA is used for core high-bandwidth digital computation. The sampling, and fast digital logic, can be clocked in the range 200 to 400 MHz, derived from an external or internal source. A custom data acquisition system, based around LabVIEW, has been developed for real-time control and monitoring at up to 460 kbps transfer rates, and is capable of writing and reading from EPICS data records. Details of the hardware, signal processing, and data acquisition will be presented. Two examples of applications will also be presented: a position and angle bunch-by-bunch feedback system using strip-line beam position monitors to stabilise intra-train positional jitter to below the micron level with a latency less than 154 ns; and a phase feedforward system using RF cavity-based phase monitors to stabilise the downstream rms phase jitter to below 50 fs with a total latency less than the 380 ns beam time-of-flight. PB - JACoW CP - Geneva, Switzerland SP - 137 EP - 140 KW - ion KW - feedback KW - kicker KW - controls KW - FPGA DA - 2017/09 PY - 2017 SN - 978-3-95450-189-2 DO - 10.18429/JACoW-PCaPAC2016-FRFMPLCO05 UR - http://jacow.org/pcapac2016/papers/frfmplco05.pdf ER -