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| WECOAA03 | FESA3 – The New Front-End Software Framework at CERN and the FAIR Facility | controls, collider, hadron | 22 | |||||
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Currently the LHC* is controlled by the use of FESA** 2.11 classes. FESA3 is not only an update of FESA2.11, but a completely new approach. GSI plans to use the FESA system at the complex FAIR facility. One of the main reasons to introduce FESA3 was to provide a framework which can be shared between different labs. This is accomplished by splitting up the FWK into a common part, which is used by all labs, and a lab-specific part, which allows e.g. a lab dependent implementation of the timing-system. FESA3 is written in C++, runs a narrow interface (RDA***), supports multiplexing of different accelerator-cycles, is completely event driven and uses thread priorities for scheduling. It provides all FESA2.11 functionalities and additionally introduces several new features. FESA3 is integrated in the Eclipse IDE as a plugin. Using this plugin, the user can easily create his FESA-class design (xml file), generate the C++ source code, fill the device-specific methods, and deploy the binary on a front end. As well as the framework the Eclipse plugin has a lab specific implementation. An operational release for FESA3 is planned end of 2010.
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* LHC = The (L)arge (H)adron (C)ollider, located at CERN/Switzerland |
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| WECOAA04 | Employing RTEMS and FPGAs for Beamline Applications at the APS | controls, photon, power-supply, instrumentation | 27 | |||||
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At the Advanced Photon Source (APS), the power and flexibility of an Altera Cyclone-II FPGA combined with the Arcturus uC5282 embedded microprocessor running RTEMS, provides a low cost solution for implementing beamline applications. In this paper, we discuss the approach of coupling an Altera FPGA and the Arcturus uC5282 to implement a time-resolved 32-channel scaler, development using the Altera Quartus-II design environment and the RTEMS tools, as well as an ASYN based EPICS device driver and its integration to the standard scaler record support. Furthermore, we discuss how this approach has been applied to other control system applications, such as for photon counting and flexible CCD shutter timing control. By employing this approach, a variety of applications can be quickly developed on one hardware platform which realizes real-time performance within the FPGA and provide a cost effective EPICS IOC for exporting data to scientists and users.
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