ICALEPCS2019 - List of Authors (Bennett, B.M.)

Paper	Title	Page
MOPHA142	FACET-II Radiation Safety Systems Development	562
	F. Tao, B.M. Bennett, N. Lipkowitz SLAC, Menlo Park, California, USA
	Facility for Advanced Accelerator Experimental Tests (FACET)-II is an upgrade of the FACET. It uses the middle third of SLAC’s 2-mile long linear accelerator to accelerate the electron beam to 10 GeV, with positron beam to be added in the Stage 2 of the project. Once the project completes in late 2019, it will be operated as a Department of Energy (DOE) user facilities for advanced accelerator science studies. In this paper, we will describe the Radiation Safety Systems (RSS) design and implementation for FACET-II project. RSS include Personnel Protection System (PPS) and Beam Containment System (BCS). Though both systems are safety critical, different technologies are used to implement safety functions. PPS uses Siemens PLC as the backbone for control but legacy CAMAC for data acquisition, while BCS develops customized electronics for faster response to protect safety devices from radiation induced damage.
	Poster MOPHA142 [1.284 MB]
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA142
About •	paper received ※ 01 October 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THCPR03	A Safety Rated FPGA Framework for Fast Safety Systems	1626
	F. Tao, B.M. Bennett, D.G. Brown, J. Jones, M.W. Stettler SLAC, Menlo Park, California, USA
	In this paper, we will introduce a generic safety-rated FPGA design template. FMEDA analysis, hardware reliability modeling, firmware development, verification and validation will be described in details to demonstrate the IEC 61508 compliant development process. In this dual redundant design, each chain consists a FPGA chip from different manufacturers to minimize the potential common cause failures. Cross checks between FPGAs and end-to-end self-checks are performed to increase the diagnostic coverage and improve the reliability. Based on this safety FPGA template, an Average Current Monitor (ACM) system is developed at SLAC with the addition of a safety PLC for diagnostics and a HMI for user interface. The overall system is deployed as part of Beam Containment System (BCS) to limit the beam current with the target Safety Integrity Level (SIL) 2.
DOI •	reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR03
About •	paper received ※ 01 October 2019 paper accepted ※ 08 October 2019 issue date ※ 30 August 2020
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

FACET-II Radiation Safety Systems Development

562

F. Tao, B.M. Bennett, N. Lipkowitz
SLAC, Menlo Park, California, USA

Facility for Advanced Accelerator Experimental Tests (FACET)-II is an upgrade of the FACET. It uses the middle third of SLAC’s 2-mile long linear accelerator to accelerate the electron beam to 10 GeV, with positron beam to be added in the Stage 2 of the project. Once the project completes in late 2019, it will be operated as a Department of Energy (DOE) user facilities for advanced accelerator science studies. In this paper, we will describe the Radiation Safety Systems (RSS) design and implementation for FACET-II project. RSS include Personnel Protection System (PPS) and Beam Containment System (BCS). Though both systems are safety critical, different technologies are used to implement safety functions. PPS uses Siemens PLC as the backbone for control but legacy CAMAC for data acquisition, while BCS develops customized electronics for faster response to protect safety devices from radiation induced damage.

Poster MOPHA142 [1.284 MB]

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-MOPHA142

About •

paper received ※ 01 October 2019 paper accepted ※ 10 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THCPR03

A Safety Rated FPGA Framework for Fast Safety Systems

1626

F. Tao, B.M. Bennett, D.G. Brown, J. Jones, M.W. Stettler
SLAC, Menlo Park, California, USA

In this paper, we will introduce a generic safety-rated FPGA design template. FMEDA analysis, hardware reliability modeling, firmware development, verification and validation will be described in details to demonstrate the IEC 61508 compliant development process. In this dual redundant design, each chain consists a FPGA chip from different manufacturers to minimize the potential common cause failures. Cross checks between FPGAs and end-to-end self-checks are performed to increase the diagnostic coverage and improve the reliability. Based on this safety FPGA template, an Average Current Monitor (ACM) system is developed at SLAC with the addition of a safety PLC for diagnostics and a HMI for user interface. The overall system is deployed as part of Beam Containment System (BCS) to limit the beam current with the target Safety Integrity Level (SIL) 2.

DOI •

reference for this paper ※ https://doi.org/10.18429/JACoW-ICALEPCS2019-THCPR03

About •

paper received ※ 01 October 2019 paper accepted ※ 08 October 2019 issue date ※ 30 August 2020

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)