ANL, Argonne, Illinois, USA
With the success and reliability of the transverse feedback system installed at the Advance Photon Source (APS), a major upgrade to expand the system is under way. The existing system is operating at a third of the storage ring bunch capacity, or 324 of the available 1296 bunches. This upgrade will allow the sampling of all 1296 bunches and make corrections for all selected bunches in a single storage ring turn. To facilitate this upgrade a new analog I/O board capable of 352 MHz operation was developed along with a revolution clock cleaning circuit. A 352MHz clock cleaning circuit was also required for the high-speed analog output circuit to maintain data integrity to the receiving DAC unit that is 61m away. This receiving DAC unit will have its transceiver data rate upgraded from 2.3Gbps to about 7Gbps transmitted over a fiber optic link. This paper discusses some of the challenges in reducing the clock jitter from both the system P0 bunch clock and the 352MHz clock along with the necessary FPGA hardware upgrades and algorithm changes, all of which is required for the success of this upgrade.
