Rauch, S.

Paper	Title	Page
TUP060	Single Board Computer for Device Control in the FAIR Accelerator Control System	1
	M. Thieme, W. Panschow, S. Rauch, M. Zweig GSI, Darmstadt
	For the FAIR accelerator control system a new single board computer (SBC) is presently under development. The SBC will be the core of the distributed intelligent peripherals and shall be realized as a multi-controller system, consisting of up to three controllers. The main components of the SBC are a powerful FPGA and a highly integrated computer-on-module (COM). FPGA and COM communicate with PCI or PCI express. With use of the COM the performance of the SBC gets flexible and scalable. If needed, the COM can be upgraded. For the communication with the controlled devices several interfaces are foreseen: A parallel bus interface (FAIR-bus), an up to 64 bit wide bidirectional interface and up to four serial high-speed links (>500 Mbit). Three Ethernet interfaces (100/1000 Mbit) are provided for the user interface to the higher control layers and general machine timing system. For diagnostic purposes the SBC holds USB, EIA-232 (RS-232) and JTAG (IEEE 1149.1). For non volatile data a compact flash interface is available.
	Poster
TUC004	The White Rabbit Project	93
	J. Serrano, P. Alvarez, M. Cattin, E. G. Cota, J. H. Lewis, P. M. Oliveira Fernandes Moreira, T. Wlostowski CERN, Geneva R. Baer, T. Fleck, M. Kreider, C. Prados, S. Rauch GSI, Darmstadt J. Dedic Cosylab, Ljubljana G. Gaderer, P. Loschmidt Austrian Academy of Sciences, Wien
	Reliable, fast and deterministic transmission of control information in a network is a need for many distributed systems. One example is timing systems, where a reference frequency is used to accurately schedule time-critical messages. The White Rabbit (WR) project is a multi-laboratory and multi-company effort to bring together the best of the data transfer and timing worlds in a completely open design. It takes advantage of the latest developments for improving timing over Ethernet, such as IEEE 1588 (Precision Time Protocol) and Synchronous Ethernet. The presented approach aims for a general purpose, fieldbus-like transmission system, which provides deterministic data and timing (sub-ns accuracy and ps jitter) to around 1000 stations. It automatically compensates for fiber lengths in the order of 10 km. This paper describes the WR design goals and the specification used for the project. It goes on to describe the central component of the WR system structure - the WR switch - with theoretical considerations about the requirements. Finally, it presents real timing measurements for the first prototypes of WR hardware.