IBIC2022 - List of Authors (De Monte, R.)

Paper	Title	Page
MOP13	Test and Measurements Results of the Pilot Tone Front End Industrialization for Elettra 2.0	51
	G. Brajnik, R. De Monte Elettra-Sincrotrone Trieste S.C.p.A., Basovizza, Italy M. Cargnelutti, U. Dragonja, P. Leban, P. Paglovec, B. Repič, A. Vigali I-Tech, Solkan, Slovenia
	Elettra 2.0 will be the low-emittance upgrade of the present machine, a third-generation lightsource based in Trieste, Italy. The new machine, foreseen to be completed in 2025-2026, will be equipped with 168 beam position readout systems divided into 12 cells. The BPM electronics will be based on the prototypes developed by the laboratory, relying on the pilot-tone compensation technique for assuring the required resolution and long-term stability. The industrialization and production of the BPM electronics system are being carried out in partnership with Instrumentation Technologies, a company that has experience with BPM readout systems within the accelerator field. This paper will present the results of the industrialization of one of BPM system’s key component: the Pilot Tone Front End, focusing on its improvements introduced on electronic and mechanical sides, giving not only a significant performance gain with respect to the previous prototype but also improving robustness and reliability. An overview of the testing procedures that will assure the performance repeatability of the series will also be provided.
	Poster MOP13 [1.295 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-IBIC2022-MOP13
About •	Received ※ 30 August 2022 — Revised ※ 09 September 2022 — Accepted ※ 11 September 2022 — Issue date ※ 05 November 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOP14	Design and Implementation of an FPGA-Based Digital Processor for BPM Applications	55
	M. Colja, S. Carrato University of Trieste, Trieste, Italy G. Brajnik, R. De Monte Elettra-Sincrotrone Trieste S.C.p.A., Basovizza, Italy
	Digital processing systems have been proven to often outperform analog elaboration. Indeed, thanks to high-density DSPs and FPGAs, operations in digital domain give results that are impossible to achieve in other ways. On the other side, dealing with this great performance and flexibility is not always straightforward: the processing chain needs to be accurately planned to reach the desired goals, avoiding erratic behaviours in the digital domain. In this paper, we focus on the design and implementation of an FPGA-based digital processor that will be used in the electron beam position monitors of Elettra 2.0. After digitizing the 500 MHz beam signals from the pickups, the system executes a digital down conversion, followed by several filtering and demodulating stages, in order to have a selectable data rate that is suitable for both diagnostics and feedback. The position calculation is also performed in FPGA as well, with the well-known difference-over-sum algorithm. According to results provided by a fixed-point simulation, the overall system has been implemented in an Intel Arria 10 FPGA, demonstrating the correct design functionality that meets the specified requirements.
	Poster MOP14 [1.475 MB]
DOI •	reference for this paper ※ doi:10.18429/JACoW-IBIC2022-MOP14
About •	Received ※ 06 September 2022 — Revised ※ 09 September 2022 — Accepted ※ 11 September 2022 — Issue date ※ 09 October 2022
Cite •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

Test and Measurements Results of the Pilot Tone Front End Industrialization for Elettra 2.0

51

G. Brajnik, R. De Monte
Elettra-Sincrotrone Trieste S.C.p.A., Basovizza, Italy
M. Cargnelutti, U. Dragonja, P. Leban, P. Paglovec, B. Repič, A. Vigali
I-Tech, Solkan, Slovenia

Elettra 2.0 will be the low-emittance upgrade of the present machine, a third-generation lightsource based in Trieste, Italy. The new machine, foreseen to be completed in 2025-2026, will be equipped with 168 beam position readout systems divided into 12 cells. The BPM electronics will be based on the prototypes developed by the laboratory, relying on the pilot-tone compensation technique for assuring the required resolution and long-term stability. The industrialization and production of the BPM electronics system are being carried out in partnership with Instrumentation Technologies, a company that has experience with BPM readout systems within the accelerator field. This paper will present the results of the industrialization of one of BPM system’s key component: the Pilot Tone Front End, focusing on its improvements introduced on electronic and mechanical sides, giving not only a significant performance gain with respect to the previous prototype but also improving robustness and reliability. An overview of the testing procedures that will assure the performance repeatability of the series will also be provided.

Poster MOP13 [1.295 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-IBIC2022-MOP13

About •

Received ※ 30 August 2022 — Revised ※ 09 September 2022 — Accepted ※ 11 September 2022 — Issue date ※ 05 November 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

MOP14

Design and Implementation of an FPGA-Based Digital Processor for BPM Applications

55

M. Colja, S. Carrato
University of Trieste, Trieste, Italy
G. Brajnik, R. De Monte
Elettra-Sincrotrone Trieste S.C.p.A., Basovizza, Italy

Digital processing systems have been proven to often outperform analog elaboration. Indeed, thanks to high-density DSPs and FPGAs, operations in digital domain give results that are impossible to achieve in other ways. On the other side, dealing with this great performance and flexibility is not always straightforward: the processing chain needs to be accurately planned to reach the desired goals, avoiding erratic behaviours in the digital domain. In this paper, we focus on the design and implementation of an FPGA-based digital processor that will be used in the electron beam position monitors of Elettra 2.0. After digitizing the 500 MHz beam signals from the pickups, the system executes a digital down conversion, followed by several filtering and demodulating stages, in order to have a selectable data rate that is suitable for both diagnostics and feedback. The position calculation is also performed in FPGA as well, with the well-known difference-over-sum algorithm. According to results provided by a fixed-point simulation, the overall system has been implemented in an Intel Arria 10 FPGA, demonstrating the correct design functionality that meets the specified requirements.

Poster MOP14 [1.475 MB]

DOI •

reference for this paper ※ doi:10.18429/JACoW-IBIC2022-MOP14

About •

Received ※ 06 September 2022 — Revised ※ 09 September 2022 — Accepted ※ 11 September 2022 — Issue date ※ 09 October 2022

Cite •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)