IBIC2016 - List of Authors (Weber, M.)

Paper	Title	Page
WEPG07	A Heterogeneous FPGA/GPU Architecture for Real-Time Data Analysis and Fast Feedback Systems	626
	M. Vogelgesang, L.E. Ardila Perez, M. Caselle, S.A. Chilingaryan, A. Kopmann, L. Rota, M. Weber KIT, Karlsruhe, Germany
	We propose a versatile and modular approach for a real-time data acquisition and evaluation system used for monitoring and feedback control in beam diagnostic and photon science experiments. Our hybrid architecture is based on an FPGA readout card* and a GPU for data processing. To increase throughput, lower latencies and reduce overall system strain, the FPGA write data directly in the GPU. After real-time data analysis the GPU writes back results either directly to the FPGA in case of fast feedback systems or to the CPU host system for storage. Communication and scheduling are handled transparently by our processing framework*. However, users can customize and extend it with their own processing plugins. Although the system is designed for real-time purposes, the modular approach also allows standalone usage for high-speed off-line analysis. We evaluated the performance of our solution measuring both processing times of data analysis algorithms used with beam instrumentation detectors as well as transfer times between FPGA and GPU. The latter suggests throughputs of up to 6.5 GB/s with latencies down to tens of microseconds, thus making it suitable for fast feedback systems. A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission, 10.1109/TNS.2015.2426877 ** A Scalable GPU-based Image Processing Framework for On-line Monitoring, 10.1109/HPCC.2012.116
	Poster WEPG07 [17.144 MB]
DOI •	reference for this paper ※ DOI:10.18429/JACoW-IBIC2016-WEPG07
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPG46	KALYPSO: A Mfps Linear Array Detector for Visible to NIR Radiation	740
	L. Rota, B.M. Balzer, M. Caselle, A.-S. Müller, M.J. Nasse, G. Niehues, P. Schönfeldt, M. Weber KIT, Eggenstein-Leopoldshafen, Germany C. Gerth, B. Steffen DESY, Hamburg, Germany N. Hiller, A. Mozzanica PSI, Villigen PSI, Switzerland D.R. Makowski, A. Mielczarek TUL-DMCS, Łódź, Poland
	Funding: This work is partially funded by the BMBF contract number: 05K16VKA. The acquisition rate of commercially available line array detectors is a bottleneck for beam diagnostics at high-repetition rate machines like synchrotron lightsources or FELs with a quasi-continuous or macro-pulse operation. In order to remove this bottleneck we have developed KALYPSO, an ultra-fast linear array detector operating at a frame-rate of up to 2.7 Mfps. The KALYPSO detector mounts InGaAs or Si linear array sensors to measure radiation in the near-infrared or visible spectrum. The FPGA-based read-out card can be connected to an external data acquisition system through a high-performance PCI-Express 3.0 data-link, allowing continuous data taking and real-time data analysis. The detector is fully synchronized with the timing system of the accelerator and other diagnostic instruments. The detector is currently installed at several accelerators: ANKA, the European XFEL and TELBE. We present the detector and the results obtained with Electro-Optical Spectral Decoding (EOSD) setups.
DOI •	reference for this paper ※ DOI:10.18429/JACoW-IBIC2016-WEPG46
Export •	reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

Paper

Title

Page

A Heterogeneous FPGA/GPU Architecture for Real-Time Data Analysis and Fast Feedback Systems

626

M. Vogelgesang, L.E. Ardila Perez, M. Caselle, S.A. Chilingaryan, A. Kopmann, L. Rota, M. Weber
KIT, Karlsruhe, Germany

We propose a versatile and modular approach for a real-time data acquisition and evaluation system used for monitoring and feedback control in beam diagnostic and photon science experiments. Our hybrid architecture is based on an FPGA readout card* and a GPU for data processing. To increase throughput, lower latencies and reduce overall system strain, the FPGA write data directly in the GPU. After real-time data analysis the GPU writes back results either directly to the FPGA in case of fast feedback systems or to the CPU host system for storage. Communication and scheduling are handled transparently by our processing framework**. However, users can customize and extend it with their own processing plugins. Although the system is designed for real-time purposes, the modular approach also allows standalone usage for high-speed off-line analysis. We evaluated the performance of our solution measuring both processing times of data analysis algorithms used with beam instrumentation detectors as well as transfer times between FPGA and GPU. The latter suggests throughputs of up to 6.5 GB/s with latencies down to tens of microseconds, thus making it suitable for fast feedback systems.
* A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission, 10.1109/TNS.2015.2426877
** A Scalable GPU-based Image Processing Framework for On-line Monitoring, 10.1109/HPCC.2012.116

Poster WEPG07 [17.144 MB]

DOI •

reference for this paper ※ DOI:10.18429/JACoW-IBIC2016-WEPG07

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

WEPG46

KALYPSO: A Mfps Linear Array Detector for Visible to NIR Radiation

740

L. Rota, B.M. Balzer, M. Caselle, A.-S. Müller, M.J. Nasse, G. Niehues, P. Schönfeldt, M. Weber
KIT, Eggenstein-Leopoldshafen, Germany
C. Gerth, B. Steffen
DESY, Hamburg, Germany
N. Hiller, A. Mozzanica
PSI, Villigen PSI, Switzerland
D.R. Makowski, A. Mielczarek
TUL-DMCS, Łódź, Poland

Funding: This work is partially funded by the BMBF contract number: 05K16VKA.
The acquisition rate of commercially available line array detectors is a bottleneck for beam diagnostics at high-repetition rate machines like synchrotron lightsources or FELs with a quasi-continuous or macro-pulse operation. In order to remove this bottleneck we have developed KALYPSO, an ultra-fast linear array detector operating at a frame-rate of up to 2.7 Mfps. The KALYPSO detector mounts InGaAs or Si linear array sensors to measure radiation in the near-infrared or visible spectrum. The FPGA-based read-out card can be connected to an external data acquisition system through a high-performance PCI-Express 3.0 data-link, allowing continuous data taking and real-time data analysis. The detector is fully synchronized with the timing system of the accelerator and other diagnostic instruments. The detector is currently installed at several accelerators: ANKA, the European XFEL and TELBE. We present the detector and the results obtained with Electro-Optical Spectral Decoding (EOSD) setups.

DOI •

reference for this paper ※ DOI:10.18429/JACoW-IBIC2016-WEPG46

Export •

reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)