Paper | Title | Page |
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TUPB32 | Design Specifications for a Radiation Tolerant Beam Loss Measurement ASIC | 243 |
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A novel radiation hardened current digitizer ASIC is in planning stage, aimed at the acquisition of the current signal from the ionization chambers employed in the Beam Loss Monitoring system in CERN accelerator chain. The purpose is to match and exceed the performances of the existing discrete component design, currently in operation in the Large Hadron Collider (LHC). The specifications include: a dynamic range of nine decades, defaulting to the 1pA-1mA range but adjustable by the user, ability to withstand a total integrated dose of at least 10 kGray in 20 years of operation and user selectable integrating windows, as low as 500ns. Moreover, the integrated circuit can be employed to digitize currents of both polarity with a minimum number of external components and without needing any configuration. The target technology is IBM 130 nm CMOS process. The specifications, the architecture choices and the reasons on which they're based upon are discussed in the paper. |
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TUPB33 | Systematic Study of Acquisition Electronics with a High Dynamic Range for a Beam Loss Measurement System | 245 |
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A discrete components design of a current digitizer based on the current-to-frequency converter (CFC) principle is currently under development at CERN. The design targets at rather high input current compared to similar designs, with a maximum equal to 200mA and a minimum of 1nA, as required by the ionization chamber that will be employed in the Proton Synchrotron and Booster accelerators as well as in the LINAC. It allows the acquisition of currents of both polarities without requiring any configuration and provides fractional counts through an ADC to increase the resolution. Several architectural choices are being considered for the front-end circuit, including charge balance integrators, dual-integrator input stages, integrators with switchable-capacitor, in both synchronous and asynchronous versions. The signal is processed by an FPGA and transmitted over a VME64x bus. Design, simulations and measurements are discussed in this article. |