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Ha, K. M.

Paper Title Page
WEPMA075 Improvement of Web-Based Monitoring of EPICS-IOC for PAL Control System 428
 
  • J. M. Kim, K. M. Ha, H.-S. Kang, J. H. Kim, E.-H. Lee
    PAL, Pohang, Kyungbuk
  
  We are now operating a web-based monitoring system of PAL control system with MAC Power PC. In order to expand the IOC’s web-based monitoring system, we are trying to use the X86/Linux platform. With the experience which we got in developing the web-based monitoring of EPICS-IOC based on MAC Power PC, a web-based monitoring system with an X86 Intel PC based on a new concept has been developed for lower costs, easier access and use. Its operating system employs Linux Fedora Cor·104. In order to drive the web-based monitoring system, EPICS Base 3.14.8 and MySQL 4.0 have been installed in the Linux Fedora Core 4. Archive engine with C language and EPICS channel access library are programmed to store the data. As a result of using the web-based monitoring system based on the X86 Intel PC, we have achieved its easier access and use, more convenient maintenance. Performance of the web-based monitoring system with an X86 Intel PC will be discussed.  
WEPMA080 Control System for the Bending MPS at PLS Linac 437
 
  • J. H. Kim, J. Choi, K. M. Ha, J. Y. Huang, H.-S. Kang, J. M. Kim, S.-C. Kim, I. S. Ko
    PAL, Pohang, Kyungbuk
  
  The former control system of the bending MPS (Magnet Power Supply) has a three-layered architecture. It was developed by in-house members in early 1993. It is upgraded based on EPICS as the protocol for the full upgrade of the PLS control system. We have replaced the former VME 68K CPU boards with OS-9 to new Power CPU boards operated by VxWorks as IOC in the linac klystron gallery. The upgraded bending MPS control system consists of a MVME5100 EPICS IOC core in the lower level control. It is implemented with the MEDM tool of EPICS to provide friendly Graphical User Interfaces. This paper describes the VME IOC and OPI and embedded local controller in MPS cabinet used for the bending MPS control in the PLS linac

Pohang Accelerator Laboratory, Pohang, 790-784, KoreaThis works supported by the Ministry of Science and Technology, Korea.

 
THPMA033 Digital Power Supply Development at the PLS 674
 
  • K. M. Ha, J. H. Kim
    PAL, Pohang, Kyungbuk
  
  Digital power supply controller using the Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) has been developed over the year at the Pohang Light Source (PLS). Recently, full digital power supply controller has been completed and tested. A new digital controller is designed as 3U euro-standard size and provides overall performance of the power supplies stability better than 5 ppm short-term stability (< 1 min) and 25 ppm long-term stability (< 12 hours). The digital controller made use of the digital PID current controller with one-pole digital filter and feed-forward voltage ripple compensation control algorithms. By implementation of the digital controller, it is capable of high step resolution (150 ps) Digital Pulse Width Modulation (DPWM) for FET or IGBT switch drivers and high resolution (18-bit, 400 kSPS) analog to digital converter (ADC) for current and voltage signal measurements. In this paper the hardware and software structure of the developed digital controller and experimental results of digital power supply are described.

Pohang Accelerator Laboratory, Pohang, 790-784, Korea* This works supported by the Ministry of Science and Technology, Korea.