PCaPAC2014 - List of Keywords (timing)

Paper	Title	Other Keywords	Page
WPO004	News from the FAIR Control System under Development	controls, software, framework, ion	37
	R. Bär, D.H. Beck, C. Betz, J. Fitzek, S. Jülicher, U. Krause, M. Thieme, R. Vincelli GSI, Darmstadt, Germany
	The control system for the FAIR (Facility for Antiproton and Ion Research) accelerator facility is presently under development and implementation. The FAIR accelerators will extend the present GSI accelerator chain, then being used as injector, and provide anti-proton, ion, and rare isotope beams with unprecedented intensity and quality for a variety of research programs. This paper shortly summarizes the general status of the FAIR project and focusses on the progress of the control system design and its implementation. The poster presents the general system architecture and updates on the status of major building blocks of the control system. We highlight the control system implementation efforts for CRYRING, a new accelerator presently under recommissioning at GSI, which will serve as a test-ground for the complete control system stack and evaluation of the new controls concepts.
	Slides WPO004 [1.039 MB]

WPO006	FESA3 Integration in GSI for FAIR	site, software, framework, controls	43
	S. Matthies, H. Bräuning, A. Schwinn GSI, Darmstadt, Germany S. Deghaye CERN, Geneva, Switzerland
	GSI decided to use FESA (Front-End Software Architecture) as the front-end software toolkit for the FAIR accelerator complex. FESA was originally developed at CERN. Since 2010 FESA3, a revised version of FESA, is developed in the frame of an international collaboration between CERN and GSI. During development of FESA3 emphasis was placed on the possibility of flexible customization for different environments and to provide site-specific extensions to allow adaptation for the contributors. GSI is the first institute different than CERN to integrate FESA3 into its control system environment. Some of the necessary preparations have already been performed to establish FESA3 at GSI. Examples are RPM packaging for multiple installations, support for site-specific properties and data types, first integration of the White Rabbit based timing system, etc. . Further developments such as e.g. integration of a site-specific database or the full integration of GSI's beam process concept for FAIR will follow.

TCO304	Launching the FAIR Timing System with CRYRING	controls, software, network, hardware	155
	M. Kreider Glyndŵr University, Wrexham, United Kingdom R. Bär, D.H. Beck, A. Hahn, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany J.N. Bai IAP, Frankfurt am Main, Germany
	During the past two years, significant progress has been made on the development of the General Machine Timing system for the upcoming FAIR facility at GSI. The prime features are time-synchronization of 2000-3000 nodes using the White Rabbit Precision-Time-Protocol (WR-PTP), distribution of International Atomic Time (TAI) time stamps and synchronized command and control of FAIR control system equipment. A White Rabbit network has been set up connecting parts of the existing facility and a next version of the Timing Master has been developed. Timing Receiver nodes in form factors Scalable Control Unit (standard front-end controller for FAIR), VME, PCIe and standalone have been developed. CRYRING is the first machine on the GSI/FAIR campus to be operated with this new timing system and serves as a test-ground for the complete control system. Installation of equipment starts in late spring followed by commissioning of equipment in summer 2014.
	Slides TCO304 [7.818 MB]

FPO022	New developments on the FAIR Data Master	controls, operation, network, FPGA	207
	M. Kreider, J. Davies, V. Grout Glyndŵr University, Wrexham, United Kingdom R. Bär, D.H. Beck, M. Kreider, W.W. Terpstra GSI, Darmstadt, Germany
	During the last year, a small scale timing system has been built with a first version of the Data Master. In this paper, we will describe field test progress as well as new design concepts and implementation details of the new prototype to be tested with the CRYRING accelerator timing system. The message management layer has been introduced as a hardware acceleration module for the timely dispatch of control messages. It consists of a priority queue for outgoing messages, combined with a scheduler and network load balancing. This loosens the real-time constraints for the CPUs composing the control messages noticeably, making the control firmware very easy to construct and deterministic. It is further opening perspectives away from the current virtual machine-like implementation on to a specialized programming language for accelerator control. In addition, a streamlined and better fitting model for beam production chains and cycles has been devised for use in the data master firmware. The processing worst case execution time becomes completely calculable, enabling fixed time-slices for safe multiplexing of cycles in all of the CPUs.
	Slides FPO022 [0.890 MB]

FPO024	First Idea on Bunch to Bucket Transfer for FAIR	target, network, synchrotron, flattop	210
	J.N. Bai IAP, Frankfurt am Main, Germany R. Bär, D.H. Beck, T. Ferrand, M. Kreider, D. Ondreka, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany
	The FAIR facility makes use of the General Machine Timing (GMT) system and the Bunch phase Timing System (BuTiS) to realize the synchronization of two machines. In order to realize the bunch to bucket transfer, firstly, the source machine slightly detunes its RF frequency at its RF flattop. Secondly, the source and target machines exchange packets over the timing network shortly before the transfer and make use of the RF frequency-beat method to realize the synchronization between both machines with accuracy better than 1o. The data of the packet includes RF frequency, timestamp of the zero-crossing point of the RF signal, harmonic number and bunch/bucket position. Finally, both machines have all information of each other and can calculate the coarse window and create announce signals for triggering kickers.
	Poster FPO024 [2.077 MB]

Paper

Title

Other Keywords

Page

WPO004

News from the FAIR Control System under Development

controls, software, framework, ion

37

R. Bär, D.H. Beck, C. Betz, J. Fitzek, S. Jülicher, U. Krause, M. Thieme, R. Vincelli
GSI, Darmstadt, Germany

The control system for the FAIR (Facility for Antiproton and Ion Research) accelerator facility is presently under development and implementation. The FAIR accelerators will extend the present GSI accelerator chain, then being used as injector, and provide anti-proton, ion, and rare isotope beams with unprecedented intensity and quality for a variety of research programs. This paper shortly summarizes the general status of the FAIR project and focusses on the progress of the control system design and its implementation. The poster presents the general system architecture and updates on the status of major building blocks of the control system. We highlight the control system implementation efforts for CRYRING, a new accelerator presently under recommissioning at GSI, which will serve as a test-ground for the complete control system stack and evaluation of the new controls concepts.

Slides WPO004 [1.039 MB]

WPO006

FESA3 Integration in GSI for FAIR

site, software, framework, controls

43

S. Matthies, H. Bräuning, A. Schwinn
GSI, Darmstadt, Germany
S. Deghaye
CERN, Geneva, Switzerland

GSI decided to use FESA (Front-End Software Architecture) as the front-end software toolkit for the FAIR accelerator complex. FESA was originally developed at CERN. Since 2010 FESA3, a revised version of FESA, is developed in the frame of an international collaboration between CERN and GSI. During development of FESA3 emphasis was placed on the possibility of flexible customization for different environments and to provide site-specific extensions to allow adaptation for the contributors. GSI is the first institute different than CERN to integrate FESA3 into its control system environment. Some of the necessary preparations have already been performed to establish FESA3 at GSI. Examples are RPM packaging for multiple installations, support for site-specific properties and data types, first integration of the White Rabbit based timing system, etc. . Further developments such as e.g. integration of a site-specific database or the full integration of GSI's beam process concept for FAIR will follow.

TCO304

Launching the FAIR Timing System with CRYRING

controls, software, network, hardware

155

M. Kreider
Glyndŵr University, Wrexham, United Kingdom
R. Bär, D.H. Beck, A. Hahn, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany
J.N. Bai
IAP, Frankfurt am Main, Germany

During the past two years, significant progress has been made on the development of the General Machine Timing system for the upcoming FAIR facility at GSI. The prime features are time-synchronization of 2000-3000 nodes using the White Rabbit Precision-Time-Protocol (WR-PTP), distribution of International Atomic Time (TAI) time stamps and synchronized command and control of FAIR control system equipment. A White Rabbit network has been set up connecting parts of the existing facility and a next version of the Timing Master has been developed. Timing Receiver nodes in form factors Scalable Control Unit (standard front-end controller for FAIR), VME, PCIe and standalone have been developed. CRYRING is the first machine on the GSI/FAIR campus to be operated with this new timing system and serves as a test-ground for the complete control system. Installation of equipment starts in late spring followed by commissioning of equipment in summer 2014.

Slides TCO304 [7.818 MB]

FPO022

New developments on the FAIR Data Master

controls, operation, network, FPGA

207

M. Kreider, J. Davies, V. Grout
Glyndŵr University, Wrexham, United Kingdom
R. Bär, D.H. Beck, M. Kreider, W.W. Terpstra
GSI, Darmstadt, Germany

During the last year, a small scale timing system has been built with a first version of the Data Master. In this paper, we will describe field test progress as well as new design concepts and implementation details of the new prototype to be tested with the CRYRING accelerator timing system. The message management layer has been introduced as a hardware acceleration module for the timely dispatch of control messages. It consists of a priority queue for outgoing messages, combined with a scheduler and network load balancing. This loosens the real-time constraints for the CPUs composing the control messages noticeably, making the control firmware very easy to construct and deterministic. It is further opening perspectives away from the current virtual machine-like implementation on to a specialized programming language for accelerator control. In addition, a streamlined and better fitting model for beam production chains and cycles has been devised for use in the data master firmware. The processing worst case execution time becomes completely calculable, enabling fixed time-slices for safe multiplexing of cycles in all of the CPUs.

Slides FPO022 [0.890 MB]

FPO024

First Idea on Bunch to Bucket Transfer for FAIR

target, network, synchrotron, flattop

210

J.N. Bai
IAP, Frankfurt am Main, Germany
R. Bär, D.H. Beck, T. Ferrand, M. Kreider, D. Ondreka, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany

The FAIR facility makes use of the General Machine Timing (GMT) system and the Bunch phase Timing System (BuTiS) to realize the synchronization of two machines. In order to realize the bunch to bucket transfer, firstly, the source machine slightly detunes its RF frequency at its RF flattop. Secondly, the source and target machines exchange packets over the timing network shortly before the transfer and make use of the RF frequency-beat method to realize the synchronization between both machines with accuracy better than 1o. The data of the packet includes RF frequency, timestamp of the zero-crossing point of the RF signal, harmonic number and bunch/bucket position. Finally, both machines have all information of each other and can calculate the coarse window and create announce signals for triggering kickers.

Poster FPO024 [2.077 MB]