PCaPAC2014 - List of Keywords (real-time)

Paper	Title	Other Keywords	Page
FPO002	Picosecond Sampling Electronics for Terahertz Synchrotron Radiation	radiation, synchrotron, synchrotron-radiation, detector	167
	C.M. Caselle, B.M. Balzer, M. Brosi, S.A. Chilingaryan, T. Dritschler, V. Judin, A. Kopmann, A.-S. Müller, L. Petzold, J. Raasch, L. Rota, M. Siegel, N.J. Smale, J.L. Steinmann, M. Vogelgesang, M. Weber, S. Wuensch KIT, Eggenstein-Leopoldshafen, Germany
	To study the synchrotron terahertz emission superconducting (YBCO) film detectors are used with the intrinsic response time in the order of a few picoseconds. For fast, continuous sampling of the individual THz ultra-short pulses a novel digitizer system has been developed. The system consists of detector, wideband low-noise amplifier, fast pulse digitizer board, back-end readout board. High-end graphic processing units (GPUs) perform real-time data analysis. Four samples with 12 bit are recorded in parallel for each fast pulse with programmable sampling times in the range of 3 to 100 ps. A new bus master DMA engine connected to PCI express endpoint has been developed to ensure a continuous high data throughput of up to 4 GByte/s. This heterogeneous real-time system architecture based on FPGA and GPU has successful been used for on-line pulse reconstruction and evaluations and calculates the peak amplitude of each pulse and the time between consecutive bunches with a picosecond time resolution at ANKA. A Fast Fourier Transform (FFT) is performed on-line for the frequency analysis of the CSR undulations.
	Slides FPO002 [1.153 MB]

FPO008	LabVIEW PCAS Interface for NI CompactRIO	interface, LabView, EPICS, software	173
	G. Liu, C. Li, J.G. Wang, K. Xuan USTC/NSRL, Hefei, Anhui, People's Republic of China K. Yang, K. Zheng National Instruments China, Shanghai, People's Republic of China
	When the NI LabVIEW EPICS Server I/O Server is used to integrate NI CompactRIO devices running under VxWorks into EPICS, we notice that it only supports "VAL" field, neither alarms nor time stamps are supported. In order to overcome these drawbacks, a new LabVIEW Channel Access Portable Server (PCAS) Interface is developed, and is applied to the Hefei Light Source (HLS) cooling water monitor system. The test results in the HLS cooling water monitor system indicate that this approach can greatly improve the performance of the NI CompactRIO devices in EPICS environment.

FPO012	A Real-Time Data Logger for the MICE Superconducting Magnets	LabView, FPGA, EPICS, controls	185
	J.T.G. Wilson STFC/DL, Daresbury, Warrington, Cheshire, United Kingdom
	The Muon Ionisation Cooling Experiment (MICE) being constructed at STFC’s Rutherford Appleton Laboratory will allow scientists to gain working experience of the design, construction and operation of a muon cooling channel. Among the key components are a number of superconducting solenoid and focus coil magnets specially designed for the MICE project and built by industrial partners. During testing it became apparent that fast, real-time logging of magnet performance before, during and after a quench was required to diagnose unexpected magnet behaviour. To this end a National Instruments Compact RIO (cRIO) data logger system was created, so that it was possible to see how the quench propagates through the magnet. The software was written in Real-Time LabVIEW and makes full use of the cRIO built-in FPGA to obtain synchronised, multi-channel data logging at rates of up to 10kHz. This paper will explain the design and capabilities of the created system, how it has helped to better understand the internal behaviour of the magnets during a quench and additional development to allow simultaneous logging of multiple magnets and integration into the existing EPICS control system.

FPO017	Managing Multiple Function Generators for FAIR	Linux, controls, software, FPGA	199
	S. Rauch, R. Bär, M. Thieme GSI, Darmstadt, Germany
	In the FAIR control system, equipment which needs to be controlled with ramped nominal values (e.g. power converters) is controlled by a standard front-end controller called scalable control unit (SCU). An SCU combines a ComExpressBoard with Intel CPU and an FPGA baseboard and acts as bus-master on the SCU host-bus. Up to 12 function generators can be implemented in slave-board FPGAs and can be controlled from one SCU. The real-time data supply for the generators demands a special software/hardware approach. Direct control of the generators with a FESA (front-end control software architecture) class, running on an Intel Atom CPU with Linux, does not meet the timing requirements. So an extra layer with an LM32 soft-core CPU is added to the FPGA. Communication between Linux and the LM32 is done via shared memory and a circular buffer data structure. The LM32 supplies the function generators with new parameter sets when it is triggered by interrupts. This two-step approach decouples the Linux CPU from the hard real-time requirements. For synchronous start and coherent clocking of all function generators, special pins on the SCU backplane are being used to avoid bus latencies.
	Poster FPO017 [1.098 MB]

Paper

Title

Other Keywords

Page

FPO002

Picosecond Sampling Electronics for Terahertz Synchrotron Radiation

radiation, synchrotron, synchrotron-radiation, detector

167

C.M. Caselle, B.M. Balzer, M. Brosi, S.A. Chilingaryan, T. Dritschler, V. Judin, A. Kopmann, A.-S. Müller, L. Petzold, J. Raasch, L. Rota, M. Siegel, N.J. Smale, J.L. Steinmann, M. Vogelgesang, M. Weber, S. Wuensch
KIT, Eggenstein-Leopoldshafen, Germany

To study the synchrotron terahertz emission superconducting (YBCO) film detectors are used with the intrinsic response time in the order of a few picoseconds. For fast, continuous sampling of the individual THz ultra-short pulses a novel digitizer system has been developed. The system consists of detector, wideband low-noise amplifier, fast pulse digitizer board, back-end readout board. High-end graphic processing units (GPUs) perform real-time data analysis. Four samples with 12 bit are recorded in parallel for each fast pulse with programmable sampling times in the range of 3 to 100 ps. A new bus master DMA engine connected to PCI express endpoint has been developed to ensure a continuous high data throughput of up to 4 GByte/s. This heterogeneous real-time system architecture based on FPGA and GPU has successful been used for on-line pulse reconstruction and evaluations and calculates the peak amplitude of each pulse and the time between consecutive bunches with a picosecond time resolution at ANKA. A Fast Fourier Transform (FFT) is performed on-line for the frequency analysis of the CSR undulations.

Slides FPO002 [1.153 MB]

FPO008

LabVIEW PCAS Interface for NI CompactRIO

interface, LabView, EPICS, software

173

G. Liu, C. Li, J.G. Wang, K. Xuan
USTC/NSRL, Hefei, Anhui, People's Republic of China
K. Yang, K. Zheng
National Instruments China, Shanghai, People's Republic of China

When the NI LabVIEW EPICS Server I/O Server is used to integrate NI CompactRIO devices running under VxWorks into EPICS, we notice that it only supports "VAL" field, neither alarms nor time stamps are supported. In order to overcome these drawbacks, a new LabVIEW Channel Access Portable Server (PCAS) Interface is developed, and is applied to the Hefei Light Source (HLS) cooling water monitor system. The test results in the HLS cooling water monitor system indicate that this approach can greatly improve the performance of the NI CompactRIO devices in EPICS environment.

FPO012

A Real-Time Data Logger for the MICE Superconducting Magnets

LabView, FPGA, EPICS, controls

185

J.T.G. Wilson
STFC/DL, Daresbury, Warrington, Cheshire, United Kingdom

The Muon Ionisation Cooling Experiment (MICE) being constructed at STFC’s Rutherford Appleton Laboratory will allow scientists to gain working experience of the design, construction and operation of a muon cooling channel. Among the key components are a number of superconducting solenoid and focus coil magnets specially designed for the MICE project and built by industrial partners. During testing it became apparent that fast, real-time logging of magnet performance before, during and after a quench was required to diagnose unexpected magnet behaviour. To this end a National Instruments Compact RIO (cRIO) data logger system was created, so that it was possible to see how the quench propagates through the magnet. The software was written in Real-Time LabVIEW and makes full use of the cRIO built-in FPGA to obtain synchronised, multi-channel data logging at rates of up to 10kHz. This paper will explain the design and capabilities of the created system, how it has helped to better understand the internal behaviour of the magnets during a quench and additional development to allow simultaneous logging of multiple magnets and integration into the existing EPICS control system.

FPO017

Managing Multiple Function Generators for FAIR

Linux, controls, software, FPGA

199

S. Rauch, R. Bär, M. Thieme
GSI, Darmstadt, Germany

In the FAIR control system, equipment which needs to be controlled with ramped nominal values (e.g. power converters) is controlled by a standard front-end controller called scalable control unit (SCU). An SCU combines a ComExpressBoard with Intel CPU and an FPGA baseboard and acts as bus-master on the SCU host-bus. Up to 12 function generators can be implemented in slave-board FPGAs and can be controlled from one SCU. The real-time data supply for the generators demands a special software/hardware approach. Direct control of the generators with a FESA (front-end control software architecture) class, running on an Intel Atom CPU with Linux, does not meet the timing requirements. So an extra layer with an LM32 soft-core CPU is added to the FPGA. Communication between Linux and the LM32 is done via shared memory and a circular buffer data structure. The LM32 supplies the function generators with new parameter sets when it is triggered by interrupts. This two-step approach decouples the Linux CPU from the hard real-time requirements. For synchronous start and coherent clocking of all function generators, special pins on the SCU backplane are being used to avoid bus latencies.

Poster FPO017 [1.098 MB]