PCaPAC2014 - Classification: Hardware Technologies

Paper

Title

Page

Inexpensive Scheduling in FPGAs

150

W.W. Terpstra, D.H. Beck, M. Kreider
GSI, Darmstadt, Germany

In the new scheme for machine control used within the FAIR project, actions are distributed to front-end controllers (FEC) with absolute execution timestamps. The execution time must be both precise to the nanosecond and scheduled faster than a microsecond, requiring a hardware solution. Although the actions are scheduled at the FEC out of order, they must be executed in sorted order. The typical hardware approaches to implementing a priority queue (CAMs, shift-registers, etc.) work well in ASIC designs, but must be implemented in expensive FPGA core logic. Conversely, the typical software approaches (heaps, calendar queues, etc.) are either too slow or too memory intensive. We present an approach which exploits the time-ordered nature of our problem to sort in constant-time using only a few memory blocks.

Slides TCO301 [1.370 MB]

TCO303

TestBed - Automated Hardware-in-the-Loop Test Framework

153

P.A. Maslov, K.A. Meyer, K. Žagar
Cosylab, Ljubljana, Slovenia

Funding: This project has received funding from the European Union’s Seventh Framework Programme for research, technological development and demonstration under grant agreement no 289485.
The control systems in big physics facilities may be updated several times a year. Ideally, prior to each release all components of the control system would be tested. One common control system component is a DAQ driver which is generally tested manually according to a predefined test plan. In order to simplify this process, we have developed the TestBed suite, a test framework that executes tests automatically. TestBed is a PXI chassis which contains an embedded controller running the control system on Scientific Linux and a DAQ board capable of generating and acquiring analog and digital signals. TestBed provides an easy-to-use framework written in Python and allows for the quick development and execution of automatic test scripts. From a hardware perspective, each system under test is physically connected to TestBed with a connector board using a predefined pin configuration. Both the system under test and TestBed are connected to the network. The resulting test framework makes it possible for the automatic tests to be executed with each new release of the control system, thus liberating human resources and ensuring complete consistency and repeatability in the testing protocol.

Slides TCO303 [0.703 MB]

TCO304

Launching the FAIR Timing System with CRYRING

155

M. Kreider
Glyndŵr University, Wrexham, United Kingdom
R. Bär, D.H. Beck, A. Hahn, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany
J.N. Bai
IAP, Frankfurt am Main, Germany

During the past two years, significant progress has been made on the development of the General Machine Timing system for the upcoming FAIR facility at GSI. The prime features are time-synchronization of 2000-3000 nodes using the White Rabbit Precision-Time-Protocol (WR-PTP), distribution of International Atomic Time (TAI) time stamps and synchronized command and control of FAIR control system equipment. A White Rabbit network has been set up connecting parts of the existing facility and a next version of the Timing Master has been developed. Timing Receiver nodes in form factors Scalable Control Unit (standard front-end controller for FAIR), VME, PCIe and standalone have been developed. CRYRING is the first machine on the GSI/FAIR campus to be operated with this new timing system and serves as a test-ground for the complete control system. Installation of equipment starts in late spring followed by commissioning of equipment in summer 2014.

Slides TCO304 [7.818 MB]

TCO305

TCP/IP Control System Interface Development Using Microchip* Brand Microcontrollers

158

C.E. Peters, M.A. Power
ANL, Argonne, Illinois, USA

Funding: This work was supported by the U.S. Department of Energy, Office of Nuclear Physics, under Contract No. DE-AC02-06CH11357.
Even as the diversity and capabilities of Single-Board-Computers (SBCs) like the Raspberry Pi and BeagleBoard continue to increase, low level microprocessor solutions also offer the possibility of robust distributed control system interfaces. Since they can be smaller and cheaper than even the least expensive SBC, they are easily integrated directly onto printed circuit boards either via direct mount or pre-installed headers. The ever increasing flash-memory capacity and processing clock speeds has enabled these types of microprocessors to handle even relatively complex tasks such as management of a full TCP/IP software and hardware stack. The purpose of this work is to demonstrate several different implementation scenarios wherein a computer control system can communicate directly with an off-the-shelf Microchip brand microcontroller and its associated peripherals. The microprocessor can act as a Hardware-to-Ethernet communication bridge and provide services such as distributed reading and writing of analog and digital values, webpage serving, simple network monitoring and others to any custom electronics solution.
* Microchip Technology Inc., www.microchip.com

Slides TCO305 [3.904 MB]

TCO306

Reconfigurable Oscilloscopes for Applications in Scientific Research

B.R. Glass
National Instruments, Austin, Texas, USA

Signal processing and control tasks in scientific research applications have traditionally relied on analog electronics and relatively slow ADCs to capture preconditioned signals. Continuous improvements in the sampling rate and resolution of commercial ADCs have allowed for an increasing number of signals to be sampled directly from sensors. With the incorporation of FPGAs, signal processing and control can be performed in real-time during acquisition. A new class of reconfigurable oscilloscopes extends the reach of PCIe-based modular instrumentation by incorporating a user-programmable FPGA for in-line signal processing, real-time control, and advanced triggering with zero dead-time. Researchers have demonstrated the power and flexibility of these instruments in recent nuclear and high-energy physics applications.

Slides TCO306 [5.559 MB]

FPO017

Managing Multiple Function Generators for FAIR

199

S. Rauch, R. Bär, M. Thieme
GSI, Darmstadt, Germany

In the FAIR control system, equipment which needs to be controlled with ramped nominal values (e.g. power converters) is controlled by a standard front-end controller called scalable control unit (SCU). An SCU combines a ComExpressBoard with Intel CPU and an FPGA baseboard and acts as bus-master on the SCU host-bus. Up to 12 function generators can be implemented in slave-board FPGAs and can be controlled from one SCU. The real-time data supply for the generators demands a special software/hardware approach. Direct control of the generators with a FESA (front-end control software architecture) class, running on an Intel Atom CPU with Linux, does not meet the timing requirements. So an extra layer with an LM32 soft-core CPU is added to the FPGA. Communication between Linux and the LM32 is done via shared memory and a circular buffer data structure. The LM32 supplies the function generators with new parameter sets when it is triggered by interrupts. This two-step approach decouples the Linux CPU from the hard real-time requirements. For synchronous start and coherent clocking of all function generators, special pins on the SCU backplane are being used to avoid bus latencies.

Poster FPO017 [1.098 MB]

FPO018

Setup and Diagnostics of Motion Control at ANKA Beamlines

201

K. Cerff, D. Haas, J. Jakel, M. Schmitt
KIT, Eggenstein-Leopoldshafen, Germany

The precise motion control in high resolution is one of the necessary conditions for making high quality measurements at beamline experiments. At a common ANKA beamline up to one hundred actuator axes are working together to align and shape beam, to select beam Energy and to position probes. Some Experiments need additional motion axes supported by transportable controllers plugged temporaly to a local beamline control system. In terms of process control all the analog and digital signals from different sources have to be verified, leveled and interfaced to the motion controllers. They have to be matched and calibrated in the control systems configuration file to real physical quantities which give the input for further data processing. A set of hard- and software tools and methods developed at ANKA over the years is presented in this paper.

Poster FPO018 [1.608 MB]

FPO019

FPGA Utilization in the Accelerator Interlock System (About the MPS Development in the LIPAc)

204

K. Nishiyama
Japan Atomic Energy Agency (JAEA), International Fusion Energy Research Center (IFERC), Rokkasho, Kamikita, Aomori, Japan
R. Gobin
CEA/IRFU, Gif-sur-Yvette, France
J. Knaster, A. Marqueta Barbero, Y. Okumura
IFMIF/EVEDA, Rokkasho, Japan
T. Kojima, T. Narita, H. Sakaki, H. Takahashi
JAEA, Aomori, Japan

The development of IFMIF (International Fusion Material Irradiation Facility) to generate a 14 MeV source of neutrons with the spectrum of DT fusion reactions is indispensable to qualify suitable materials for the First Wall of the nuclear vessel in fusion power plants. As part of IFMIF validation activities , LIPAc (Linear IFMIF Prototype Accelerator) facility, currently under installation at Rokkasho (Japan) , will accelerate a 125mA CW and 9MeV deuteron beam with a total beam power of 1.125MW. The Machine Protection System (MPS) of LIPAc provides an essential interlock function of stopping the beam in case of anomalous beam loss or other hazardous situations. High speed processing is necessary to achieve properly the MPS main goal. This high speed processing of the signals, distributed alongside the accelerator facility, is based on FPGA technology. This paper describes the basis of FPGA use in the accelerator interlock system through the development of LIPAc’s MPS, with a comparison with using of FPGA of the other accelerator control system.

FPO022

New developments on the FAIR Data Master

207

FPI03

use link to see paper's listing under its alternate paper code

M. Kreider, J. Davies, V. Grout
Glyndŵr University, Wrexham, United Kingdom
R. Bär, D.H. Beck, M. Kreider, W.W. Terpstra
GSI, Darmstadt, Germany

During the last year, a small scale timing system has been built with a first version of the Data Master. In this paper, we will describe field test progress as well as new design concepts and implementation details of the new prototype to be tested with the CRYRING accelerator timing system. The message management layer has been introduced as a hardware acceleration module for the timely dispatch of control messages. It consists of a priority queue for outgoing messages, combined with a scheduler and network load balancing. This loosens the real-time constraints for the CPUs composing the control messages noticeably, making the control firmware very easy to construct and deterministic. It is further opening perspectives away from the current virtual machine-like implementation on to a specialized programming language for accelerator control. In addition, a streamlined and better fitting model for beam production chains and cycles has been devised for use in the data master firmware. The processing worst case execution time becomes completely calculable, enabling fixed time-slices for safe multiplexing of cycles in all of the CPUs.

Slides FPO022 [0.890 MB]

FPO024

First Idea on Bunch to Bucket Transfer for FAIR

210

J.N. Bai
IAP, Frankfurt am Main, Germany
R. Bär, D.H. Beck, T. Ferrand, M. Kreider, D. Ondreka, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig
GSI, Darmstadt, Germany

The FAIR facility makes use of the General Machine Timing (GMT) system and the Bunch phase Timing System (BuTiS) to realize the synchronization of two machines. In order to realize the bunch to bucket transfer, firstly, the source machine slightly detunes its RF frequency at its RF flattop. Secondly, the source and target machines exchange packets over the timing network shortly before the transfer and make use of the RF frequency-beat method to realize the synchronization between both machines with accuracy better than 1o. The data of the packet includes RF frequency, timestamp of the zero-crossing point of the RF signal, harmonic number and bunch/bucket position. Finally, both machines have all information of each other and can calculate the coarse window and create announce signals for triggering kickers.

Poster FPO024 [2.077 MB]

Paper	Title	Page
TCO301	Inexpensive Scheduling in FPGAs	150
	W.W. Terpstra, D.H. Beck, M. Kreider GSI, Darmstadt, Germany
	In the new scheme for machine control used within the FAIR project, actions are distributed to front-end controllers (FEC) with absolute execution timestamps. The execution time must be both precise to the nanosecond and scheduled faster than a microsecond, requiring a hardware solution. Although the actions are scheduled at the FEC out of order, they must be executed in sorted order. The typical hardware approaches to implementing a priority queue (CAMs, shift-registers, etc.) work well in ASIC designs, but must be implemented in expensive FPGA core logic. Conversely, the typical software approaches (heaps, calendar queues, etc.) are either too slow or too memory intensive. We present an approach which exploits the time-ordered nature of our problem to sort in constant-time using only a few memory blocks.
	Slides TCO301 [1.370 MB]

TCO303	TestBed - Automated Hardware-in-the-Loop Test Framework	153
	P.A. Maslov, K.A. Meyer, K. Žagar Cosylab, Ljubljana, Slovenia
	Funding: This project has received funding from the European Union’s Seventh Framework Programme for research, technological development and demonstration under grant agreement no 289485. The control systems in big physics facilities may be updated several times a year. Ideally, prior to each release all components of the control system would be tested. One common control system component is a DAQ driver which is generally tested manually according to a predefined test plan. In order to simplify this process, we have developed the TestBed suite, a test framework that executes tests automatically. TestBed is a PXI chassis which contains an embedded controller running the control system on Scientific Linux and a DAQ board capable of generating and acquiring analog and digital signals. TestBed provides an easy-to-use framework written in Python and allows for the quick development and execution of automatic test scripts. From a hardware perspective, each system under test is physically connected to TestBed with a connector board using a predefined pin configuration. Both the system under test and TestBed are connected to the network. The resulting test framework makes it possible for the automatic tests to be executed with each new release of the control system, thus liberating human resources and ensuring complete consistency and repeatability in the testing protocol.
	Slides TCO303 [0.703 MB]

TCO304	Launching the FAIR Timing System with CRYRING	155
	M. Kreider Glyndŵr University, Wrexham, United Kingdom R. Bär, D.H. Beck, A. Hahn, M. Kreider, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany J.N. Bai IAP, Frankfurt am Main, Germany
	During the past two years, significant progress has been made on the development of the General Machine Timing system for the upcoming FAIR facility at GSI. The prime features are time-synchronization of 2000-3000 nodes using the White Rabbit Precision-Time-Protocol (WR-PTP), distribution of International Atomic Time (TAI) time stamps and synchronized command and control of FAIR control system equipment. A White Rabbit network has been set up connecting parts of the existing facility and a next version of the Timing Master has been developed. Timing Receiver nodes in form factors Scalable Control Unit (standard front-end controller for FAIR), VME, PCIe and standalone have been developed. CRYRING is the first machine on the GSI/FAIR campus to be operated with this new timing system and serves as a test-ground for the complete control system. Installation of equipment starts in late spring followed by commissioning of equipment in summer 2014.
	Slides TCO304 [7.818 MB]

TCO305	TCP/IP Control System Interface Development Using Microchip* Brand Microcontrollers	158
	C.E. Peters, M.A. Power ANL, Argonne, Illinois, USA
	Funding: This work was supported by the U.S. Department of Energy, Office of Nuclear Physics, under Contract No. DE-AC02-06CH11357. Even as the diversity and capabilities of Single-Board-Computers (SBCs) like the Raspberry Pi and BeagleBoard continue to increase, low level microprocessor solutions also offer the possibility of robust distributed control system interfaces. Since they can be smaller and cheaper than even the least expensive SBC, they are easily integrated directly onto printed circuit boards either via direct mount or pre-installed headers. The ever increasing flash-memory capacity and processing clock speeds has enabled these types of microprocessors to handle even relatively complex tasks such as management of a full TCP/IP software and hardware stack. The purpose of this work is to demonstrate several different implementation scenarios wherein a computer control system can communicate directly with an off-the-shelf Microchip brand microcontroller and its associated peripherals. The microprocessor can act as a Hardware-to-Ethernet communication bridge and provide services such as distributed reading and writing of analog and digital values, webpage serving, simple network monitoring and others to any custom electronics solution. * Microchip Technology Inc., www.microchip.com
	Slides TCO305 [3.904 MB]

TCO306	Reconfigurable Oscilloscopes for Applications in Scientific Research
	B.R. Glass National Instruments, Austin, Texas, USA
	Signal processing and control tasks in scientific research applications have traditionally relied on analog electronics and relatively slow ADCs to capture preconditioned signals. Continuous improvements in the sampling rate and resolution of commercial ADCs have allowed for an increasing number of signals to be sampled directly from sensors. With the incorporation of FPGAs, signal processing and control can be performed in real-time during acquisition. A new class of reconfigurable oscilloscopes extends the reach of PCIe-based modular instrumentation by incorporating a user-programmable FPGA for in-line signal processing, real-time control, and advanced triggering with zero dead-time. Researchers have demonstrated the power and flexibility of these instruments in recent nuclear and high-energy physics applications.
	Slides TCO306 [5.559 MB]

FPO017	Managing Multiple Function Generators for FAIR	199
	S. Rauch, R. Bär, M. Thieme GSI, Darmstadt, Germany
	In the FAIR control system, equipment which needs to be controlled with ramped nominal values (e.g. power converters) is controlled by a standard front-end controller called scalable control unit (SCU). An SCU combines a ComExpressBoard with Intel CPU and an FPGA baseboard and acts as bus-master on the SCU host-bus. Up to 12 function generators can be implemented in slave-board FPGAs and can be controlled from one SCU. The real-time data supply for the generators demands a special software/hardware approach. Direct control of the generators with a FESA (front-end control software architecture) class, running on an Intel Atom CPU with Linux, does not meet the timing requirements. So an extra layer with an LM32 soft-core CPU is added to the FPGA. Communication between Linux and the LM32 is done via shared memory and a circular buffer data structure. The LM32 supplies the function generators with new parameter sets when it is triggered by interrupts. This two-step approach decouples the Linux CPU from the hard real-time requirements. For synchronous start and coherent clocking of all function generators, special pins on the SCU backplane are being used to avoid bus latencies.
	Poster FPO017 [1.098 MB]

FPO018	Setup and Diagnostics of Motion Control at ANKA Beamlines	201
	K. Cerff, D. Haas, J. Jakel, M. Schmitt KIT, Eggenstein-Leopoldshafen, Germany
	The precise motion control in high resolution is one of the necessary conditions for making high quality measurements at beamline experiments. At a common ANKA beamline up to one hundred actuator axes are working together to align and shape beam, to select beam Energy and to position probes. Some Experiments need additional motion axes supported by transportable controllers plugged temporaly to a local beamline control system. In terms of process control all the analog and digital signals from different sources have to be verified, leveled and interfaced to the motion controllers. They have to be matched and calibrated in the control systems configuration file to real physical quantities which give the input for further data processing. A set of hard- and software tools and methods developed at ANKA over the years is presented in this paper.
	Poster FPO018 [1.608 MB]

FPO019	FPGA Utilization in the Accelerator Interlock System (About the MPS Development in the LIPAc)	204
	K. Nishiyama Japan Atomic Energy Agency (JAEA), International Fusion Energy Research Center (IFERC), Rokkasho, Kamikita, Aomori, Japan R. Gobin CEA/IRFU, Gif-sur-Yvette, France J. Knaster, A. Marqueta Barbero, Y. Okumura IFMIF/EVEDA, Rokkasho, Japan T. Kojima, T. Narita, H. Sakaki, H. Takahashi JAEA, Aomori, Japan
	The development of IFMIF (International Fusion Material Irradiation Facility) to generate a 14 MeV source of neutrons with the spectrum of DT fusion reactions is indispensable to qualify suitable materials for the First Wall of the nuclear vessel in fusion power plants. As part of IFMIF validation activities , LIPAc (Linear IFMIF Prototype Accelerator) facility, currently under installation at Rokkasho (Japan) , will accelerate a 125mA CW and 9MeV deuteron beam with a total beam power of 1.125MW. The Machine Protection System (MPS) of LIPAc provides an essential interlock function of stopping the beam in case of anomalous beam loss or other hazardous situations. High speed processing is necessary to achieve properly the MPS main goal. This high speed processing of the signals, distributed alongside the accelerator facility, is based on FPGA technology. This paper describes the basis of FPGA use in the accelerator interlock system through the development of LIPAc’s MPS, with a comparison with using of FPGA of the other accelerator control system.

FPO022	New developments on the FAIR Data Master	207
FPI03	use link to see paper's listing under its alternate paper code
	M. Kreider, J. Davies, V. Grout Glyndŵr University, Wrexham, United Kingdom R. Bär, D.H. Beck, M. Kreider, W.W. Terpstra GSI, Darmstadt, Germany
	During the last year, a small scale timing system has been built with a first version of the Data Master. In this paper, we will describe field test progress as well as new design concepts and implementation details of the new prototype to be tested with the CRYRING accelerator timing system. The message management layer has been introduced as a hardware acceleration module for the timely dispatch of control messages. It consists of a priority queue for outgoing messages, combined with a scheduler and network load balancing. This loosens the real-time constraints for the CPUs composing the control messages noticeably, making the control firmware very easy to construct and deterministic. It is further opening perspectives away from the current virtual machine-like implementation on to a specialized programming language for accelerator control. In addition, a streamlined and better fitting model for beam production chains and cycles has been devised for use in the data master firmware. The processing worst case execution time becomes completely calculable, enabling fixed time-slices for safe multiplexing of cycles in all of the CPUs.
	Slides FPO022 [0.890 MB]

FPO024	First Idea on Bunch to Bucket Transfer for FAIR	210
	J.N. Bai IAP, Frankfurt am Main, Germany R. Bär, D.H. Beck, T. Ferrand, M. Kreider, D. Ondreka, C. Prados, S. Rauch, W.W. Terpstra, M. Zweig GSI, Darmstadt, Germany
	The FAIR facility makes use of the General Machine Timing (GMT) system and the Bunch phase Timing System (BuTiS) to realize the synchronization of two machines. In order to realize the bunch to bucket transfer, firstly, the source machine slightly detunes its RF frequency at its RF flattop. Secondly, the source and target machines exchange packets over the timing network shortly before the transfer and make use of the RF frequency-beat method to realize the synchronization between both machines with accuracy better than 1o. The data of the packet includes RF frequency, timestamp of the zero-crossing point of the RF signal, harmonic number and bunch/bucket position. Finally, both machines have all information of each other and can calculate the coarse window and create announce signals for triggering kickers.
	Poster FPO024 [2.077 MB]