SLAC, Menlo Park, California
ANL, Argonne
Funding: Work supported by U.S. Department of Energy under Contract Nos. DE-AC02-06CH11357 and DE-AC02-76SF00515.
We present the performance of the cavity beam position monitor (BPM) system for the LCLS undulator. The construction and installation phase of 34 BPMs for the undulator and 2 for the transport line have been completed. The X-band cavity BPM employs a TM010 monopole reference cavity and a TM110 dipole cavity designed to operate at a center frequency of 11.384 GHz. The signal processing electronics features a low-noise single-stage three-channel heterodyne receiver that has selectable gain and a phase locking local oscillator. The approximately 40 MHz IF is digitized by a 120M sample/second four-channel 16-bit digitizer. System requirements include sub-micron position resolution for a single-bunch beam charge of 200 pC. We discuss the system specifications and commissioning results.
SLAC, Menlo Park, California
Funding: SLAC/DOE Contract DE-AC02-76-SF00515
A state-of-the-art Machine Protection System for the SLAC Linac Coherent Light Source has been designed and built to shut off the beam within one pulse during 120 Hz operation to protect the facility from damage due to beam losses. Inputs from beam loss monitors, BPMs, toroids and position switches of insertable beam line devices are connected to a number of Link Node chassis placed along the beam line. Link Nodes are connected with a central Link Processor in a star topology on a dedicated gigabit Ethernet fiber network. The Link Processor, a Motorola MVME 6100, processes fault data at 360 Hz. After processing, rate limit commands are sent to mitigation devices at the injector and just upstream of the entrance of the sensitive undulator beam line. The beam's repetition rate is lowered according to the fault severity. The SLAC designed Link Nodes support up to 96 digital inputs and 8 digital outputs each. Analog signals are handled via standard IndustryPack (IP) cards placed on the Link Node motherboards with optional transition boards for signal conditioning. A database driven algorithm running on the Link Processor provides runtime loadable and swappable machine protection logic.