PAC09 - List of Authors (Fors, T.)

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Fors, T.

Paper	Title	Page
TU6RFP002	A High-Resolution DPWM Generation Topology for Digitally Controlled Precision DC/DC Converters at the APS	1535
	G. Feng, B. Deriy, T. Fors, J. Wang ANL, Argonne
	Funding: Work supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357. The APS storage ring uses DC/DC converters to power the magnets. High resolution for current regulation is desired for future improvement. It is calculated that at least 20- to 21-bit digital pulse width modulation (DPWM) is required in the proposed digital control system. This paper proposes a digital control system that adopts a new DPWM topology to achieve 21-bit DPWM without gigahertz system clock. The proposed topology uses a combination of a field-programmable gate array (FPGA) and a serializer chip TLK2541 from TI. The FPGA calculates the desired PWM signals and sends them to the TLK2541 chip. Then, the TLK2541 generates corresponding high-resolution DPWM pulses. An FPGA development board has been used to develop a prototype system to verify the proposed DPWM generation topology. This paper discusses the circuit topology and the experiment results.

Paper

Title

Page

TU6RFP002

A High-Resolution DPWM Generation Topology for Digitally Controlled Precision DC/DC Converters at the APS

1535

G. Feng, B. Deriy, T. Fors, J. Wang
ANL, Argonne

Funding: Work supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.

The APS storage ring uses DC/DC converters to power the magnets. High resolution for current regulation is desired for future improvement. It is calculated that at least 20- to 21-bit digital pulse width modulation (DPWM) is required in the proposed digital control system. This paper proposes a digital control system that adopts a new DPWM topology to achieve 21-bit DPWM without gigahertz system clock. The proposed topology uses a combination of a field-programmable gate array (FPGA) and a serializer chip TLK2541 from TI. The FPGA calculates the desired PWM signals and sends them to the TLK2541 chip. Then, the TLK2541 generates corresponding high-resolution DPWM pulses. An FPGA development board has been used to develop a prototype system to verify the proposed DPWM generation topology. This paper discusses the circuit topology and the experiment results.