PAC09 - List of Authors (Feng, S.)

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Feng, S.

Paper	Title	Page
TU6RFP068	Test of the Prototype Module of PTS	1705
	H.T. Li, J. Deng, S. Feng, M. Xia, W. Xie CAEP/IFP, Mainyang, Sichuan
	Funding: Hongtao Li is with the Institute of Fluid Physics, China Academy of Engineering Physics (CAEP), Mianyang City, Sichuan, China. (Fax:86-816-2282695; e-mail: lht680526@ 21cn.com). In order to study the physics of fast Z-pinches and research the key issues of pulse power technology, a 10MA/6MV z-pinch primary test stand (PTS) composed of 24 modules will be built in IFP. The prototype module adopted capacitive storage scheme is composed of the 6MV/300kJ Marx-generator (MG), intermediate storage capacitor (IC), laser-triggered switch (LTS), pulse forming line (PFL), water self-breakdown switch (WS), and tri-plate pulse transmission line (PTL). The measured output current of the prototype is approximate 520kA, and output voltage is approximate 2.1MV. The unique multi-stage LTS based on uniform field distribution design and multi-pin unsymmetrical WS make the prototype modules have low systemic delay jitter which is necessary for synchronization of multi-module facility. 1-δ jitter of delay of the system is less than 4ns.

Paper

Title

Page

TU6RFP068

Test of the Prototype Module of PTS

1705

H.T. Li, J. Deng, S. Feng, M. Xia, W. Xie
CAEP/IFP, Mainyang, Sichuan

Funding: Hongtao Li is with the Institute of Fluid Physics, China Academy of Engineering Physics (CAEP), Mianyang City, Sichuan, China. (Fax:86-816-2282695; e-mail: lht680526@ 21cn.com).

In order to study the physics of fast Z-pinches and research the key issues of pulse power technology, a 10MA/6MV z-pinch primary test stand (PTS) composed of 24 modules will be built in IFP. The prototype module adopted capacitive storage scheme is composed of the 6MV/300kJ Marx-generator (MG), intermediate storage capacitor (IC), laser-triggered switch (LTS), pulse forming line (PFL), water self-breakdown switch (WS), and tri-plate pulse transmission line (PTL). The measured output current of the prototype is approximate 520kA, and output voltage is approximate 2.1MV. The unique multi-stage LTS based on uniform field distribution design and multi-pin unsymmetrical WS make the prototype modules have low systemic delay jitter which is necessary for synchronization of multi-module facility. 1-δ jitter of delay of the system is less than 4ns.