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Deriy, B.

Paper Title Page
TU6RFP001 The New-Generation Power Supplies for the Circular Polarized Undulator at the APS 1532
 
  • B. Deriy, A.L. Hillman, J. Wang
    ANL, Argonne
  
 

Funding: Work supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.


The Circular Polarizing Undulator (CPU) had been used for about 10 years at the APS to generate X-rays with variable polarization (circular and linear) switching at rates up to 10 Hz. The CPU consists of two main coils with maximal currents 1600A (about 30kW power) and 400A (4kW power) and seven additional correcting coils. Aging and obsolescence of some of the CPU PS critical components resulted in deterioration of its performance and elevated maintenance. To resolve the issue and to comply with the new requirements for the beam stability at the APS storage ring, the new PS and control electronics for the CPU have been proposed. The new 8-channel Arbitrary Function Generator generating unique complex waveforms for the correctors to minimize orbit distortion during the main coils PS switching will also be discussed in this paper.

  
TU6RFP002 A High-Resolution DPWM Generation Topology for Digitally Controlled Precision DC/DC Converters at the APS 1535
 
  • G. Feng, B. Deriy, T. Fors, J. Wang
    ANL, Argonne
  
 

Funding: Work supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.


The APS storage ring uses DC/DC converters to power the magnets. High resolution for current regulation is desired for future improvement. It is calculated that at least 20- to 21-bit digital pulse width modulation (DPWM) is required in the proposed digital control system. This paper proposes a digital control system that adopts a new DPWM topology to achieve 21-bit DPWM without gigahertz system clock. The proposed topology uses a combination of a field-programmable gate array (FPGA) and a serializer chip TLK2541 from TI. The FPGA calculates the desired PWM signals and sends them to the TLK2541 chip. Then, the TLK2541 generates corresponding high-resolution DPWM pulses. An FPGA development board has been used to develop a prototype system to verify the proposed DPWM generation topology. This paper discusses the circuit topology and the experiment results.