PAC09 - List of Authors (Dedic, J.)

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Dedic, J. [Dedič, J.]

Paper	Title	Page
TH6REP087	Firmware Development for SNS New Timing Master	4162
	R. Štefanič, J. Dedič Cosylab, Ljubljana D. Curry ORNL RAD, Oak Ridge, Tennessee D.H. Thompson ORNL, Oak Ridge, Tennessee
	Funding: This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the U.S. Department of Energy. Implementation of a timing system master device is a complicated task, since a lot of details have to be taken into account even once the architecture decisions have been laid down. At SNS/ORNL timing master controller is being upgraded in collaboration with Cosylab and this paper focuses on some details of its implementation. New timing system master device is based on agile FPGA circuitry and the main focus of this paper is its firmware implementation. Provided are implementation details for event distribution supporting multiple event sources and priorities. Discussed are mechanisms, ensuring deterministic behavior, different methods of encoding that have been employed, and host-independent distribution of time stamp frames. The concept of the super-cycle is explained and its implementation is laid down. Taken into account that implementation for such a complex device involves extensive testing, paper provides insight into verification it was applied. Advantages of the SystemC based test-benches over traditional VHDL-only verification are discussed.

Paper

Title

Page

TH6REP087

Firmware Development for SNS New Timing Master

4162

R. Štefanič, J. Dedič
Cosylab, Ljubljana
D. Curry
ORNL RAD, Oak Ridge, Tennessee
D.H. Thompson
ORNL, Oak Ridge, Tennessee

Funding: This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the U.S. Department of Energy.

Implementation of a timing system master device is a complicated task, since a lot of details have to be taken into account even once the architecture decisions have been laid down. At SNS/ORNL timing master controller is being upgraded in collaboration with Cosylab and this paper focuses on some details of its implementation. New timing system master device is based on agile FPGA circuitry and the main focus of this paper is its firmware implementation. Provided are implementation details for event distribution supporting multiple event sources and priorities. Discussed are mechanisms, ensuring deterministic behavior, different methods of encoding that have been employed, and host-independent distribution of time stamp frames. The concept of the super-cycle is explained and its implementation is laid down. Taken into account that implementation for such a complex device involves extensive testing, paper provides insight into verification it was applied. Advantages of the SystemC based test-benches over traditional VHDL-only verification are discussed.