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Lee, Y.S.

Paper Title Page
MOP093 Design of Low Level RF Control System for Accelerator 274
 
  • Y.S. Lee, J.-S. Chai
    SKKU, Suwon
  • K.R. Kim, K.-H. Park
    PAL, Pohang, Kyungbuk
 
 

The low level RF (LLRF) control system for PLS is being upgraded to improve the performance of the system. The LLRF control system under development consists of FPGA, and high speed ADC and DAC as well as analog front-end devices which process the signal from cavity and to RF high power system. In addition, it utilizes digital signal processing technology based on FPGA. In order to optimize the accelerating electric field in the cavity, it is required to maintain field stability less than ±1% in amplitude and 1° in phase. And the resonance condition of the cavity should be monitored and controlled. The various digital signal processing theories such as digital filters, Cordic, PI control enable to meet these requirements and to control the feedback signal less than a microsecond. The LLRF control system is also equipped with the Ethernet by the cPCI. The preliminary design study on the LLRF control system for PLS superconducting cavity will be described in this paper.