• M. Liu, D.K. Liu, C.X. Yin, L.Y. Zhao
  SINAP, Shanghai

Currently, the real-time data transfer system is widely implemented in the accelerator control system. If timing system and real-time data transfer system could be combined into one uniform system, it would be convenient to build distributed feedback system, fast interlock system and so on. So, a new timing system, the real-time synchronized data bus is developed to realize this idea. The architecture of the system and the hardware prototype design are introduced in the paper. The data exchange mechanism and system specification, including timing trigger synchronization accuracy, timing jitter relative to RF clock, data transfer rate and latency are described in detail. Redundant topology structure and fiber length compensation are specially considered. In the end, the results of testing in lab are presented.