SLAC, Menlo Park, California
SLAC National Accelerator Laboratory has built and is currently operating a first generation prototype Marx klystron modulator to meet ILC specifications. Under development is a second generation prototype, aimed at improving overall performance, serviceability, and manufacturability as compared to its predecessor. It is designed around 32 cells, each operating at 3.75 kV and correcting for its own capacitor droop. Due to the uniqueness of this application, high voltage gate drivers needed to be developed for the main 6.5 kV and droop correction 1.7 kV IGBTs. The gate driver provides vital functions such as protection of the IGBT from over-voltage and over-current, detection of gate-emitter open and short circuit conditions, and monitoring of IGBT degradation (based on collector-emitter saturation voltage). Gate drive control, diagnostic processing capabilities, and communication are digitally implemented using an FPGA. This paper details the design of the gate driver circuitry, component selection, and construction layout. In addition, experimental results are included to illustrate the effectiveness of the protection circuit.
SLAC, Menlo Park, California
A Marx-topology klystron modulator is under development for the International Linear Collider (ILC) project*. It is envisioned as a lower cost, smaller footprint, and higher reliability alternative to the present, bouncer-topology, baseline design. The application requires 120 kV (±0.5%), 140 A, 1.6 ms pulses at a rate of 5 Hz. The Marx constructs the high voltage pulse by combining, in series, a number of lower voltage cells. The Marx employs solid state elements; IGBTs and diodes, to control the charge, discharge and isolation of the cells. Active compensation of the output is used to achieve the voltage regulation while minimizing the stored energy. The developmental testing of a first generation prototype, P1, has been completed. This modulator has been integrated into a test stand with a 10 MW L-band klystron, where each is undergoing life testing. Development of a second generation prototype, P2, is underway. The P2 is based on the P1 topology but incorporates an alternative cell configuration to increase redundancy and improve availability. Status updates for both prototypes are presented.
* ILC Reference Design Report, http://www.linearcollider.org/cms/?pid=1000437
