• M. Liu, D.K. Liu, C.X. Yin, L.Y. Zhao
  SINAP, Shanghai

Cur­rent­ly, the re­al-time data trans­fer sys­tem is wide­ly im­ple­ment­ed in the ac­cel­er­a­tor con­trol sys­tem. If tim­ing sys­tem and re­al-time data trans­fer sys­tem could be com­bined into one uni­form sys­tem, it would be con­ve­nient to build dis­tribut­ed feed­back sys­tem, fast in­ter­lock sys­tem and so on. So, a new tim­ing sys­tem, the re­al-time syn­chro­nized data bus is de­vel­oped to re­al­ize this idea. The ar­chi­tec­ture of the sys­tem and the hard­ware pro­to­type de­sign are in­tro­duced in the paper. The data ex­change mech­a­nism and sys­tem spec­i­fi­ca­tion, in­clud­ing tim­ing trig­ger syn­chro­niza­tion ac­cu­ra­cy, tim­ing jit­ter rel­a­tive to RF clock, data trans­fer rate and la­ten­cy are de­scribed in de­tail. Re­dun­dant topol­o­gy struc­ture and fiber length com­pen­sa­tion are spe­cial­ly con­sid­ered. In the end, the re­sults of test­ing in lab are pre­sent­ed.