Author: Van Trappen, P.
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MOPGF121 Stripping Foil Displacement Unit Control for H− Injection in PSB at CERN 363
 
  • P. Van Trappen, R. Noulibos, W.J.M. Weterings
    CERN, Geneva, Switzerland
  
  For CERN's Linac4 (L4) Pro­ton Syn­chro­tron Booster (PSB) in­jec­tion scheme, slices of the 160 MeV H− beam will be dis­trib­uted to the 4 su­per­posed syn­chro­tron rings of the PSB. The beam will then be in­jected hor­i­zon­tally into the PSB by means of an H− charge-ex­change in­jec­tion sys­tem using a graphite strip­ping foil to strip the elec­trons from the H− ions. The foil and its po­si­tion­ing mech­a­nism will be housed under vac­uum in­side a strip­ping foil unit, con­tain­ing a set of six foils that can be me­chan­i­cally ro­tated into the beam aper­ture. The band with mounted foils is con­trolled by a step­ping motor while a re­solver, mi­cro-switches and a mem­brane po­ten­tiome­ter pro­vide foil po­si­tion feed­back. The vicin­ity of the ion­iz­ing beam and vac­uum re­quire­ments have con­strained the se­lec­tion of the above men­tioned con­trol sys­tem parts. The po­si­tion­ing and in­ter­lock­ing logic is im­ple­mented in an in­dus­trial Pro­gram­ma­ble Logic Con­troller (PLC). This paper de­scribes the de­sign of the strip­ping foil unit elec­tron­ics and con­trols and pre­sents the first re­sults ob­tained from a test bench unit which will be in­stalled in the Linac4 trans­fer line by the end of the 2015 for foil tests with beam.  
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MOPGF122 A Fast Interlock Detection System for High-Power Switch Protection 367
 
  • P. Van Trappen, E. Carlier, S. Uyttenhove
    CERN, Geneva, Switzerland
  
  Fast pulsed kicker mag­net sys­tems are pow­ered by high-volt­age and high-cur­rent pulse gen­er­a­tors with ad­justable pulse length and am­pli­tude. To de­liver this power, fast high-volt­age switches such as thyra­trons and GTOs are used to con­trol the fast dis­charge of pre-stored en­ergy. To pro­tect the ma­chine and the gen­er­a­tor it­self against in­ter­nal fail­ures of these switches sev­eral types of fast in­ter­locks sys­tems are used at TE-ABT (CERN Tech­nol­ogy de­part­ment, Ac­cel­er­a­tor Beam Trans­fer). To get rid of this het­ero­ge­neous sit­u­a­tion, a mod­u­lar dig­i­tal Fast In­ter­lock De­tec­tion Sys­tem (FIDS) has been de­vel­oped in order to re­place the ex­ist­ing fast in­ter­locks sys­tems. In ad­di­tion to the ex­ist­ing func­tion­al­ity, the FIDS sys­tem will offer new func­tion­al­i­ties such as ex­tended flex­i­bil­ity, im­proved mod­u­lar­ity, in­creased sur­veil­lance and di­ag­nos­tics, con­tem­po­rary com­mu­ni­ca­tion pro­to­cols and au­to­mated card pa­ram­e­triza­tion. A Xil­inx Zynq®-7000 SoC has been se­lected for im­ple­men­ta­tion of the re­quired func­tion­al­i­ties so that the FPGA (Field Pro­gram­ma­ble Gate Array) can hold the fast de­tec­tion and in­ter­lock­ing logic while the ARM® proces­sors allow for a flex­i­ble in­te­gra­tion in CERN's Front-End Soft­ware Ar­chi­tec­ture (FESA) frame­work, ad­vanced di­ag­nos­tics and au­to­mated self-pa­ram­e­triza­tion.  
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