ICALEPCS2015 - List of Authors (Terpstra, W.W.)

Paper	Title	Page
WEPGF119	Bunch to Bucket Transfer System for FAIR	980
	J.N. Bai IAP, Frankfurt am Main, Germany R. Bär, D. Beck, O.K. Kester, D. Ondreka, C. Prados, W.W. Terpstra GSI, Darmstadt, Germany T. Ferrand TEMF, TU Darmstadt, Darmstadt, Germany
	For the FAIR accelerator complex, synchronization of the bunch to bucket (B2B) transfer will be realized by the General Machine Timing system and the Low-Level RF system. Based on these two systems, both synchronization methods, the phase shift and the frequency beating method, are available for the B2B transfer system for FAIR. This system is capable to realize the B2B transfer within 10ms and the precision better than 1 degree for ions over the whole range of stable isotopes. At first, this system will be used for the transfer from the SIS18 to the SIS100. It will then be extended to all transfers at the FAIR accelerator facility. This paper introduces the synchronization methods and concentrates on the standard procedures and the functional blocks of the B2B transfer system.
	Poster WEPGF119 [1.493 MB]
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THHA2O03	Message Signalled Interrupts in Mixed-Master Control	1083
	W.W. Terpstra, M. Kreider GSI, Darmstadt, Germany
	Timing Receivers in the FAIR control system are a complex composition of multiple bus-connected components. The bus is composed of Wishbone crossbars which connect master devices to their controlled slaves. These crossbars are in turn connected in master-slave relationships forming a DAG where source nodes are masters, interior nodes are crossbars, and terminal nodes are slaves. In current designs, masters may be found at multiple levels in the composed bus. Bus masters range from embeddedμcontrollers, to DMA controllers, to bridges from PCIe, VME, USB, or the network. In such a system, delivery of interrupts from controlled slaves to masters is non-trivial. The master may reside multiple levels up the hierarchy. In the case of network control, the master may be kilometres of fibre away. Our approach is to use message signalled interrupts (MSI). This is especially important as a particular slave may be controlled by different masters depending on the use-case. MSI allows the routing of interrupts via the same topology used in master-slave control. This paper explores the benefits, disadvantages, and challenges uncovered by our current implementation.
	Slides THHA2O03 [0.762 MB]
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Paper

Title

Page

Bunch to Bucket Transfer System for FAIR

980

J.N. Bai
IAP, Frankfurt am Main, Germany
R. Bär, D. Beck, O.K. Kester, D. Ondreka, C. Prados, W.W. Terpstra
GSI, Darmstadt, Germany
T. Ferrand
TEMF, TU Darmstadt, Darmstadt, Germany

For the FAIR accelerator complex, synchronization of the bunch to bucket (B2B) transfer will be realized by the General Machine Timing system and the Low-Level RF system. Based on these two systems, both synchronization methods, the phase shift and the frequency beating method, are available for the B2B transfer system for FAIR. This system is capable to realize the B2B transfer within 10ms and the precision better than 1 degree for ions over the whole range of stable isotopes. At first, this system will be used for the transfer from the SIS18 to the SIS100. It will then be extended to all transfers at the FAIR accelerator facility. This paper introduces the synchronization methods and concentrates on the standard procedures and the functional blocks of the B2B transfer system.

Poster WEPGF119 [1.493 MB]

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reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)

THHA2O03

Message Signalled Interrupts in Mixed-Master Control

1083

W.W. Terpstra, M. Kreider
GSI, Darmstadt, Germany

Timing Receivers in the FAIR control system are a complex composition of multiple bus-connected components. The bus is composed of Wishbone crossbars which connect master devices to their controlled slaves. These crossbars are in turn connected in master-slave relationships forming a DAG where source nodes are masters, interior nodes are crossbars, and terminal nodes are slaves. In current designs, masters may be found at multiple levels in the composed bus. Bus masters range from embeddedμcontrollers, to DMA controllers, to bridges from PCIe, VME, USB, or the network. In such a system, delivery of interrupts from controlled slaves to masters is non-trivial. The master may reside multiple levels up the hierarchy. In the case of network control, the master may be kilometres of fibre away. Our approach is to use message signalled interrupts (MSI). This is especially important as a particular slave may be controlled by different masters depending on the use-case. MSI allows the routing of interrupts via the same topology used in master-slave control. This paper explores the benefits, disadvantages, and challenges uncovered by our current implementation.

Slides THHA2O03 [0.762 MB]

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reference for this paper using ※ BibTeX, ※ LaTeX, ※ Text/Word, ※ RIS, ※ EndNote (xml)